公开(公告)号：US5813030A

公开(公告)日：1998-09-22

申请号：US850370

申请日：1997-05-02

Applicant: Michael Eugene Tubbs

Inventor： Michael Eugene Tubbs

IPC: G06F12/08 ,  G06F12/00

CPC classification number: G06F12/0884

Abstract: A processing system includes a cache memory system which receives an address and a memory request from a processor. Simultaneously, information is accessed responsive to the address from a main memory and from a cache memory. During access of the information from the main memory and cache memory, it is determined whether the desired information is stored in the cache memory. If so, the information is output from the cache memory; if not, the information is output from the main memory.

Abstract translation: 处理系统包括从处理器接收地址和存储器请求的高速缓存存储器系统。 同时，响应于来自主存储器和高速缓冲存储器的地址访问信息。 在从主存储器和高速缓冲存储器访问信息期间，确定所需信息是否存储在高速缓冲存储器中。 如果是，则从高速缓冲存储器输出信息; 如果不是，则从主存储器输出信息。