公开(公告)号：US07369070B1

公开(公告)日：2008-05-06

申请号：US11583264

申请日：2006-10-19

申请人： Michael A. Vetsch

发明人： Michael A. Vetsch

IPC分类号： H03M7/20

CPC分类号： G01R19/2509 ,  G06F3/05

摘要： A system and method for converting analog signals to digital signals minimize the latency of the analog to digital conversion for real-time systems. The conversion system and method implements the hardware of an analog to digital converter input/output (I/O) board and a software-based I/O-driver in an expansion bus. The hardware of the ADC I/O board executes free-running conversion of an analog signal into digital form and stores the converted values in a first level of a buffer having two levels. Previously stored converted values are pushed to the second level of the buffer when a new value is written to the first level. The I/O driver then retrieves stored values from the second level of the buffer when needed by the real-time system and gates the buffer to prevent pushing during retrieval of values from the second level.

摘要翻译： 用于将模拟信号转换为数字信号的系统和方法使实时系统的模数转换的延迟最小化。 转换系统和方法在扩展总线中实现模数转换器输入/输出（I / O）板和基于软件的I / O驱动器的硬件。 ADC I / O板的硬件执行自由运行的模拟信号到数字形式的转换，并将转换的值存储在具有两个级别的缓冲器的第一级中。 当新值写入第一级时，先前存储的转换值将被推送到缓冲区的第二级。 然后，当实时系统需要时，I / O驱动器从缓冲器的第二级检索存储的值，并且在缓冲器检测到来自第二级的值时，缓冲缓冲器以防止推送。

公开(公告)号：US07983879B1

公开(公告)日：2011-07-19

申请号：US11893623

申请日：2007-08-15

申请人： Michael A. Vetsch ,  Rajiv Ghosh-Roy

发明人： Michael A. Vetsch ,  Rajiv Ghosh-Roy

IPC分类号： G06F7/60 ,  G06F17/10

CPC分类号： G06F8/34 ,  G06F11/323 ,  G06F11/3476 ,  G06F11/3612

摘要： A mechanism for configuring an inspection component in a real-time model is disclosed. The inspection component includes user-configurable parameters that control the acquisition of data for the real-time model. The data acquisition and logging logic is set up using graphical blocks that are part of the larger real-time application model. When code generation is done for the model, the data acquisition logic is also automatically generated, and runs as part of the execution of a real-time task.

摘要翻译： 公开了一种用于在实时模型中配置检查部件的机构。 检查部件包括用户可配置的参数，用于控制实时模型的数据采集。 使用作为更大实时应用程序模型的一部分的图形块设置数据采集和记录逻辑。 当为模型完成代码生成时，数据采集逻辑也自动生成，并作为执行实时任务的一部分运行。

公开(公告)号：US07609192B1

公开(公告)日：2009-10-27

申请号：US11881330

申请日：2007-07-26

申请人： Michael A. Vetsch

发明人： Michael A. Vetsch

IPC分类号： H03M1/12

CPC分类号： G01R19/2509 ,  G06F3/05

摘要： A system and method for converting analog signals to digital signals minimize the latency of the analog to digital conversion for real-time systems. The conversion system and method implements the hardware of an analog to digital converter input/output (I/O) board and a software-based I/O-driver in an expansion bus. The hardware of the ADC I/O board executes free-running conversion of an analog signal into digital form and stores the converted values in a first level of a buffer having two levels. Previously stored converted values are pushed to the second level of the buffer when a new value is written to the first level. The I/O driver then retrieves stored values from the second level of the buffer when needed by the real-time system and gates the buffer to prevent pushing during retrieval of values from the second level.

摘要翻译： 用于将模拟信号转换为数字信号的系统和方法使实时系统的模数转换的延迟最小化。 转换系统和方法在扩展总线中实现模数转换器输入/输出（I / O）板和基于软件的I / O驱动器的硬件。 ADC I / O板的硬件执行自由运行的模拟信号到数字形式的转换，并将转换的值存储在具有两个级别的缓冲器的第一级中。 当新值写入第一级时，先前存储的转换值将被推送到缓冲区的第二级。 然后，当实时系统需要时，I / O驱动器从缓冲器的第二级检索存储的值，并且在缓冲器检测到来自第二级的值时，缓冲缓冲器以防止推送。

公开(公告)号：US07170433B1

公开(公告)日：2007-01-30

申请号：US11157294

申请日：2005-06-20

申请人： Michael A. Vetsch

发明人： Michael A. Vetsch

IPC分类号： H03M1/06

CPC分类号： G01R19/2509 ,  G06F3/05

摘要： A system and method for converting analog signals to digital signals minimize the latency of the analog to digital conversion for real-time systems. The conversion system and method implements the hardware of an analog to digital converter input/output (I/O) board and a software-based I/O-driver in an expansion bus. The hardware of the ADC I/O board executes free-running conversion of an analog signal into digital form and stores the converted values in a first level of a buffer having two levels. Previously stored converted values are pushed to the second level of the buffer when a new value is written to the first level. The I/O driver then retrieves stored values from the second level of the buffer when needed by the real-time system and gates the buffer to prevent pushing during retrieval of values from the second level.

摘要翻译： 用于将模拟信号转换为数字信号的系统和方法使实时系统的模数转换的延迟最小化。 转换系统和方法在扩展总线中实现模拟数字转换器输入/输出（I / O）板和基于软件的I / O驱动器的硬件。 ADC I / O板的硬件执行自由运行的模拟信号到数字形式的转换，并将转换的值存储在具有两个级别的缓冲器的第一级中。 当新值写入第一级时，先前存储的转换值将被推送到缓冲区的第二级。 然后，当实时系统需要时，I / O驱动器从缓冲器的第二级检索存储的值，并且在缓冲器检测到来自第二级的值时，缓冲缓冲器以防止推送。

公开(公告)号：US07420486B1

公开(公告)日：2008-09-02

申请号：US11583184

申请日：2006-10-19

申请人： Michael A. Vetsch

发明人： Michael A. Vetsch

IPC分类号： H03M7/20

CPC分类号： G01R19/2509 ,  G06F3/05

摘要： A system and method for converting analog signals to digital signals minimize the latency of the analog to digital conversion for real-time systems. The conversion system and method implements the hardware of an analog to digital converter input/output (I/O) board and a software-based I/O-driver in an expansion bus. The hardware of the ADC I/O board executes free-running conversion of an analog signal into digital form and stores the converted values in a first level of a buffer having two levels. Previously stored converted values are pushed to the second level of the buffer when a new value is written to the first level. The I/O driver then retrieves stored values from the second level of the buffer when needed by the real-time system and gates the buffer to prevent pushing during retrieval of values from the second level.