Packet processing graphs
    2.
    发明授权

    公开(公告)号:US11323378B2

    公开(公告)日:2022-05-03

    申请号:US16539089

    申请日:2019-08-13

    Abstract: A packet processing system comprises a packet processing graph comprising classifier nodes including a root classifier node and leaf classifier nodes. The root classifier node is connected to each of the classifier nodes through a respective packet processing path in the graph. Each classifier node stores node match data indicative of at least one match to be applied by the respective classifier node. The classifier nodes comprise first and second classifier nodes arranged in a first packet processing path of said plurality of packet processing paths. The first classifier node stores node match data indicative of a match corresponding to content from a plurality of packet header field types, including first and second, different packet header field types. The second classifier node stores node match data indicative of a match corresponding to content from at least one packet header field type, including the first packet header field type.

    Generating packet processing graphs

    公开(公告)号:US11423084B2

    公开(公告)日:2022-08-23

    申请号:US16539186

    申请日:2019-08-13

    Abstract: A graph data structure for a packet processing system is generated. The structure comprises graph data objects representing classifier nodes of a packet processing graph. The classifier nodes include a root node and leaf nodes. The root node is connected to each of the leaf nodes through respective corresponding packet processing paths through the graph. Each graph data object includes node match data indicative of at least one match to be applied by the respective classifier node. One or more n-type match graph data objects are identified, which include node match data indicative of an n-type match corresponding to content from n header field types. One or more (n+m)-type match graph data objects are identified, which include node match data indicative of an (n+m)-type match corresponding to a combination of content from a (n+m) different header field types. n and m are integer values of 1 or more.

    Packet processing graphs
    4.
    发明授权

    公开(公告)号:US12003421B2

    公开(公告)日:2024-06-04

    申请号:US17732959

    申请日:2022-04-29

    Abstract: A packet processing system comprises a packet processing graph comprising classifier nodes including a root classifier node and leaf classifier nodes. The root classifier node is connected to each of the classifier nodes through a respective packet processing path in the graph. Each classifier node stores node match data indicative of at least one match to be applied by the respective classifier node. The classifier nodes comprise first and second classifier nodes arranged in a first packet processing path of said plurality of packet processing paths. The first classifier node stores node match data indicative of a match corresponding to content from a plurality of packet header field types, including first and second, different packet header field types. The second classifier node stores node match data indicative of a match corresponding to content from at least one packet header field type, including the first packet header field type.

    Resource allocation
    6.
    发明授权

    公开(公告)号:US09665408B2

    公开(公告)日:2017-05-30

    申请号:US14567938

    申请日:2014-12-11

    CPC classification number: G06F9/5088 H04L65/1023 H04L65/403 H04L65/608

    Abstract: Certain examples are described relating to resource allocation for one or more digital signal processors in a media gateway. Processing of telecommunication calls are allocated to different digital signal processor cores in the media gateway. When more processing resources are required for a call, a determination is made as to whether any of a set of digital signal processor cores are able to provide these resources. Responsive to a particular digital signal processor core being unable to provide the further processing resources, a reallocation process is initiated. This may involve reserving resources on a further digital processor core, releasing the original set of processing resources and allocating the processing of the call to the further digital processor core.

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