公开(公告)号：US10341147B1

公开(公告)日：2019-07-02

申请号：US15890285

申请日：2018-02-06

Applicant: MegaChips Corporation

Inventor： Abhishek Kumar Khare ,  Raghavendra R. G ,  Anil Chawda ,  Shubham Srivastava

IPC: H04B1/16 ,  H04L25/03 ,  H04L12/26

Abstract: A high performance equalization method is disclosed for achieving low deterministic jitter across Process, Voltage and Temperature (PVT) for various channel lengths and data rates. The method includes receiving input signal at front end of a receiver upon passing through a channel, generating with an eye-opening monitor circuit a control code based on channel conditions, and equalizing with a continuous-time linear equalization equalizer (CTLE) circuit the input signal based on the control code such that the eye-opening monitor circuit and the CTLE circuit are biased based on their corresponding replica circuits, and the control code is generated in a feedforward configuration.