公开(公告)号：US20220129729A1

公开(公告)日：2022-04-28

申请号：US17571542

申请日：2022-01-10

Applicant: MegaChips Corporation

Inventor： Mahito MATSUMOTO ,  Koji ISHIO ,  Hironobu FUJIYOSHI

IPC: G06N3/04 ,  G06F17/16 ,  G06F7/544

Abstract: Provided is a processor for a neural network whose high-performance compact model can be incorporated into low-spec devices such as embedded devices or mobile devices without requiring re-training. The processor for a neural network, which uses a multi-valued basis matrix, widens the range of integer values that can be taken by each element of the multi-valued basis matrix; thus, the number of dimensions (the number of elements) of a scaling coefficient vector is reduced accordingly. The elements of the scaling coefficient vector are real numbers, and thus reducing the amount of processing of real number calculation processing allows for reducing the number of dimensions (the number of elements) of the scaling coefficient vector. As a result, this neural network processor significantly reduces the amount of calculation processing while ensuring the calculation accuracy when performing matrix calculation processing using the binary basis matrix.