公开(公告)号：US08717079B2

公开(公告)日：2014-05-06

申请号：US13908700

申请日：2013-06-03

Applicant: MediaTek Inc.

Inventor： Cheng-Hsing Chien ,  Yung-Chieh Yu ,  Jia-Yi Xu

IPC: H03K3/356 ,  H03K3/00

CPC classification number: H03K3/356147 ,  H03K3/012 ,  H03K3/356156

Abstract: The invention provides a flip-flop. In one embodiment, the flip-flop receives a low swing clock signal, and comprises a first NMOS transistor, a first latch circuit, a second NMOS transistor, and a second latch circuit. The low swing clock signal is inverted to obtain an inverted low swing clock signal. The first NMOS transistor is coupled between a receiving node and a first node, and has a gate coupled to the inverted low swing clock signal. The first latch circuit is coupled between the first node and a second node. The second NMOS transistor is coupled between the second node and a third node. The second latch circuit is coupled between the third node and a fourth node, and generates an output signal on the fourth node.

Abstract translation: 本发明提供一种触发器。 在一个实施例中，触发器接收低摆频时钟信号，并且包括第一NMOS晶体管，第一锁存电路，第二NMOS晶体管和第二锁存电路。 低摆频时钟信号被反相以获得反相的低摆频时钟信号。 第一NMOS晶体管耦合在接收节点和第一节点之间，并且具有耦合到反相低摆频时钟信号的栅极。 第一锁存电路耦合在第一节点和第二节点之间。 第二NMOS晶体管耦合在第二节点和第三节点之间。 第二锁存电路耦合在第三节点和第四节点之间，并且在第四节点上产生输出信号。