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公开(公告)号:US09722746B2
公开(公告)日:2017-08-01
申请号:US15165088
申请日:2016-05-26
Applicant: MediaTek Inc.
Inventor: Stacy Ho , Wei-Hsin Tseng
CPC classification number: H04L5/0041 , H03M1/0617 , H03M1/466 , H03M3/406 , H03M3/41 , H03M3/426 , H03M3/47 , H04B1/0075 , H04B1/123 , H04L5/001 , H04L27/2647
Abstract: Methods and apparatus for providing bandpass analog to digital conversion (ADC) in RF receiver circuitry of a wireless-communication device. The bandpass ADC includes first noise-shaping successive approximation register (NS-SAR) circuitry arranged in a first path and second NS-SAR circuitry arranged in a second path parallel to the first path, wherein the first and second NS-SAR circuitries are configured to alternately sample an analog input voltage at a particular sampling rate and to output a digital voltage at the particular sampling rate.
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公开(公告)号:US20170085349A1
公开(公告)日:2017-03-23
申请号:US15165088
申请日:2016-05-26
Applicant: MediaTek Inc.
Inventor: Stacy Ho , Wei-Hsin Tseng
CPC classification number: H04L5/0041 , H03M1/0617 , H03M1/466 , H03M3/406 , H03M3/41 , H03M3/426 , H03M3/47 , H04B1/0075 , H04B1/123 , H04L5/001 , H04L27/2647
Abstract: Methods and apparatus for providing bandpass analog to digital conversion (ADC) in RF receiver circuitry of a wireless-communication device. The bandpass ADC includes first noise-shaping successive approximation register (NS-SAR) circuitry arranged in a first path and second NS-SAR circuitry arranged in a second path parallel to the first path, wherein the first and second NS-SAR circuitries are configured to alternately sample an analog input voltage at a particular sampling rate and to output a digital voltage at the particular sampling rate.
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公开(公告)号:US10483947B2
公开(公告)日:2019-11-19
申请号:US16157165
申请日:2018-10-11
Applicant: MEDIATEK Inc.
Inventor: Tien-Yu Lo , Chan-Hsiang Weng , Patrick Cooney , Tsung-Kai Kao , Stacy Ho
Abstract: The invention provides an anti-aliasing filter (AAF) for discretization at a sampling period. The AAF may include an operational amplifier having an input terminal and an output terminal, a first capacitor coupled between the input terminal and the output terminal, a second capacitor, and a first switch coupled between the first capacitor and the second capacitor. During a first phase, the first switch may conduct the second capacitor to the first capacitor. During a second phase, the first switch may stop conducting the second capacitor to the first capacitor. The first phase may last for one said sampling period.
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