公开(公告)号：US20240152671A1

公开(公告)日：2024-05-09

申请号：US18501044

申请日：2023-11-03

Applicant: MEDIATEK INC.

Inventor： Chi-Ming Lee ,  Chung-An Wang ,  Cheok Yan Goh ,  Chia-Cheng Tsai ,  Chien-Hsin Yeh ,  Chia-Shun Yeh ,  Chin-Tang Lai

IPC: G06F30/27

CPC classification number: G06F30/27

Abstract: A violation checking method includes generating a violation log report for a design, classifying violation logs in the violation log report into high-risk logs and low-risk logs by a machine learning model, reviewing the high-risk logs, and modifying the design if at least one bug is identified in the high-risk logs.

公开(公告)号：US12025653B2

公开(公告)日：2024-07-02

申请号：US17968798

申请日：2022-10-19

Applicant: MEDIATEK INC.

Inventor： Chung-An Wang ,  Chiao-Hua Tseng ,  Chia-Cheng Tsai ,  Tung-Yu Lee ,  Yen-Her Chen ,  Chien-Hsin Yeh ,  Chia-Shun Yeh ,  Chin-Tang Lai

IPC: G01R31/28

CPC classification number: G01R31/2837 ,  G01R31/2841

Abstract: An artificial intelligence (AI)-based constrained random verification (CRV) method for a design under test (DUT) includes: receiving a series of constraints; obtaining a limited constraint range according to the series of constraints; generating a series of stimuli according to the limited constraint range; and verifying the DUT by the series of stimuli; wherein at least one of the step of obtaining the limited constraint range according to the series of constraints and the step of generating the series of stimuli according to the limited constraint range employs an AI algorithm.

公开(公告)号：US20220138570A1

公开(公告)日：2022-05-05

申请号：US17495489

申请日：2021-10-06

Applicant: MediaTek Inc.

Inventor： Chia-Yu Tsai ,  Hung-Hao Shen ,  Chen-Feng Chiang ,  Chung-An Wang ,  Yiju Ting ,  Chia-Shun Yeh ,  Chin-Tang Lai ,  Feng-Ming Tsai ,  Kai-En Yang

IPC: G06N3/08

Abstract: A system performs the operations of a neural network agent and a circuit simulator for analog circuit sizing. The system receives an input indicating a specification of an analog circuit and design parameters. The system iteratively searches a design space until a circuit size is found to satisfy the specification and the design parameters. In each iteration, the neural network agent calculates measurement estimates for random sample generated in a trust region, which is a portion of the design space. Based on the measurement estimate, the system identifies a candidate size that optimizes a value metric. The circuit simulator receives the candidate size and generates a simulation measurement. The system calculates updates to weights of the neural network agent and the trust region for a next iteration based on, at least in part, the simulation measurement.

公开(公告)号：US20250147863A1

公开(公告)日：2025-05-08

申请号：US18935662

申请日：2024-11-04

Applicant: MEDIATEK INC.

Inventor： Min-Shan Huang ,  Hui-Chi Kuo ,  Wei-Geng Fan ,  Chin-Tang Lai ,  Chiang-Lin Lu ,  Chia-Shun Yeh

IPC: G06F11/36 ,  G06N3/0475 ,  G06N20/20

Abstract: A method of performing code review and a code review system are provided. The code review system includes a code repository, a static scanning tool, an analytical neural network and a generative neural network. The code repository is configured to store an original source code and a new code created by a developer in response to a code change request to merge the new code with the original source code. The static scanning tool is configured to collect data associated with each commit in the new code. The analytical neural network is implemented with an analytical AI and configured to assess a risk level of each commit in the new code. The generative neural network is implemented with a generative AI and configured to provide a code summarization and an initial code review comment of each commit in the new code.

公开(公告)号：US20250054130A1

公开(公告)日：2025-02-13

申请号：US18798858

申请日：2024-08-09

Applicant: MEDIATEK INC.

Inventor： En Jen ,  Shao-Yun Liu ,  Yi-Ju Ting ,  Chin-Tang Lai ,  Chia-Shun Yeh ,  Ching-Yu Lin ,  Ching-Han Jan ,  Po-Hsuan Huang

IPC: G06T7/00 ,  G06V10/762

Abstract: A wafer map recognition method using artificial intelligence includes obtaining wafer maps of a plurality of wafers; performing an unsupervised algorithm on the wafer map of each wafer in the plurality of wafers to generate a feature data set for the corresponding wafer map; and performing a clustering algorithm according to a plurality of feature data sets for the plurality of wafer maps to find a wafer map with a potential defect.

公开(公告)号：US20230144389A1

公开(公告)日：2023-05-11

申请号：US17968798

申请日：2022-10-19

Applicant: MEDIATEK INC.

Inventor： Chung-An Wang ,  Chiao-Hua Tseng ,  Chia-Cheng Tsai ,  Tung-Yu Lee ,  Yen-Her Chen ,  Chien-Hsin Yeh ,  Chia-Shun Yeh ,  Chin-Tang Lai

IPC: G01R31/28

CPC classification number: G01R31/2837 ,  G01R31/2841

Abstract: An artificial intelligence (AI)-based constrained random verification (CRV) method for a design under test (DUT) includes: receiving a series of constraints; obtaining a limited constraint range according to the series of constraints; generating a series of stimuli according to the limited constraint range; and verifying the DUT by the series of stimuli; wherein at least one of the step of obtaining the limited constraint range according to the series of constraints and the step of generating the series of stimuli according to the limited constraint range employs an AI algorithm.