公开(公告)号：US20070245326A1

公开(公告)日：2007-10-18

申请号：US11538601

申请日：2006-10-04

申请人： Masato Tatsuoka ,  Atsushi Ike

发明人： Masato Tatsuoka ,  Atsushi Ike

IPC分类号： G06F9/45 ,  G06F9/44

CPC分类号： G06F8/44 ,  G06F17/5022 ,  G06F17/5045 ,  G06F2217/86

摘要： A SW/HW partitioning and evaluating program allows a computer to perform a procedure of compiling a source code in which a mark is added to a portion to be executed by hardware, a procedure of generating an executable program for a simulator of CPU on a SoC, a procedure of storing in memory an execution result of the executable program, and a procedure of evaluating an SW/HW partition based on the execution result.

摘要翻译： SW / HW分区和评估程序允许计算机执行编译其中将标记添加到要由硬件执行的部分的源代码的过程，在SoC上为CPU的模拟器生成可执行程序的过程 ，在存储器中存储可执行程序的执行结果的程序，以及基于执行结果来评估SW / HW分区的过程。

公开(公告)号：US07496490B2

公开(公告)日：2009-02-24

申请号：US11362828

申请日：2006-02-28

申请人： Masato Tatsuoka ,  Atsushi Ike

发明人： Masato Tatsuoka ,  Atsushi Ike

IPC分类号： G06F9/455

CPC分类号： G06F17/5022 ,  G06F9/52 ,  G06F2217/86

摘要： Core model processing of a processor model PE1 and a processor model PE2 is serialized. Therefore, processing time for the inter-core-model communication is required between the core model processing of a first processor model and the core model processing of a second processor model. The inter-core-model communication processing is performed such that the inter-core-model communication required for the simulation processing of a multi-processor model is performed in parallel with the core model processing.

摘要翻译： 将处理器型号PE1和处理器型号PE2的核心模型处理序列化。 因此，在第一处理器模型的核心模型处理和第二处理器模型的核心模型处理之间需要用于核心间模型通信的处理时间。 执行核心间模型通信处理，使得与核心模型处理并行执行多处理器模型的模拟处理所需的核心间模型通信。

公开(公告)号：US20070233451A1

公开(公告)日：2007-10-04

申请号：US11439124

申请日：2006-05-24

申请人： Masato Tatsuoka ,  Atsushi Ike

发明人： Masato Tatsuoka ,  Atsushi Ike

IPC分类号： G06F9/45

CPC分类号： G06F8/49

摘要： It is determined whether an i-th instruction is for a memory access. If the i-th instruction is the memory access, it is determined whether an address to access according to the i-th instruction coincides with an address that has been accessed by a first execution block. If the addresses coincide with each other, it is determined whether a cycle of a second execution block currently executing precedes that of the first execution block. If the cycle of the second execution block precedes that of the first executing block, a memory model is accessed. A necessary number of cycles for execution of a j-th instruction is added to the current number of cycles, and the address, a cycle, data, and a data size at the time of the current access (before re-writing) are written in a delay table.

摘要翻译： 确定第i条指令是否用于存储器访问。 如果第i条指令是存储器访问，则确定根据第i条指令访问的地址是否与已由第一执行块访问的地址一致。 如果地址彼此一致，则确定当前执行的第二执行块的周期是否先于第一执行块的周期。 如果第二执行块的周期先于第一执行块的周期，则访问存储器模型。 用于执行第j指令的必要数量的循环被添加到当前循环次数中，并且写入当前访问时（重写前）的地址，周期，数据和数据大小被写入 在延迟表中。

公开(公告)号：US20070038429A1

公开(公告)日：2007-02-15

申请号：US11336967

申请日：2006-01-23

申请人： Masato Tatsuoka ,  Atsushi Ike

发明人： Masato Tatsuoka ,  Atsushi Ike

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F2217/86

摘要： A system simulation method preventing the simulation speed from lowering. An initialization section allocates an area corresponding to a certain area on a memory model to be accessed by a user hardware model, as a user hardware memory, on a computer memory. Memory access from the user hardware model is always made to the user hardware memory. An access control section enables memory access from a processor core model to the user hardware memory and controls the memory access so that no conflict occurs with the access from the user hardware model.

摘要翻译： 一种防止模拟速度降低的系统仿真方法。 初始化部分将计算机存储器上的作为用户硬件存储器的用户硬件模型访问的存储器模型上的特定区域对应的区域分配。 来自用户硬件模型的内存访问总是对用户硬件内存进行。 访问控制部分使得能够从处理器核心模型到用户硬件存储器的存储器访问，并且控制存储器访问，使得与用户硬件模型的访问不会发生冲突。

公开(公告)号：US07908592B2

公开(公告)日：2011-03-15

申请号：US11538601

申请日：2006-10-04

申请人： Masato Tatsuoka ,  Atsushi Ike

发明人： Masato Tatsuoka ,  Atsushi Ike

IPC分类号： G06F9/44 ,  G06F9/45

CPC分类号： G06F8/44 ,  G06F17/5022 ,  G06F17/5045 ,  G06F2217/86

摘要： A software/hardware (SW/HW) partitioning and evaluating program allows a computer to perform a procedure of compiling a source code in which a mark is added to a portion to be executed by hardware, a procedure of generating an executable program for a simulator of CPU on a system-on-chip (SoC), a procedure of storing in memory an execution result of the executable program, and a procedure of evaluating an SW/HW partition based on the execution result.

摘要翻译： 软件/硬件（SW / HW）分区和评估程序允许计算机执行编译源代码的过程，其中将标记添加到要由硬件执行的部分，生成用于模拟器的可执行程序的过程 （SoC）上的CPU的存储器，存储可执行程序的执行结果的过程以及基于执行结果来评估SW / HW分区的过程。

公开(公告)号：US07729896B2

公开(公告)日：2010-06-01

申请号：US11439124

申请日：2006-05-24

申请人： Masato Tatsuoka ,  Atsushi Ike

发明人： Masato Tatsuoka ,  Atsushi Ike

IPC分类号： G06F17/50

CPC分类号： G06F8/49

摘要： It is determined whether an i-th instruction is for a memory access. If the i-th instruction is the memory access, it is determined whether an address to access according to the i-th instruction coincides with an address that has been accessed by a first execution block. If the addresses coincide with each other, it is determined whether a cycle of a second execution block currently executing precedes that of the first execution block. If the cycle of the second execution block precedes that of the first executing block, a memory model is accessed. A necessary number of cycles for execution of a j-th instruction is added to the current number of cycles, and the address, a cycle, data, and a data size at the time of the current access (before re-writing) are written in a delay table.

摘要翻译： 确定第i条指令是否用于存储器访问。 如果第i条指令是存储器访问，则确定根据第i条指令访问的地址是否与已由第一执行块访问的地址一致。 如果地址彼此一致，则确定当前执行的第二执行块的周期是否先于第一执行块的周期。 如果第二执行块的周期先于第一执行块的周期，则访问存储器模型。 用于执行第j指令的必要数量的循环被添加到当前循环次数中，并且写入当前访问时（重写前）的地址，周期，数据和数据大小被写入 在延迟表中。

公开(公告)号：US20090037888A1

公开(公告)日：2009-02-05

申请号：US12213871

申请日：2008-06-25

申请人： Masato Tatsuoka ,  Atsushi Ike

发明人： Masato Tatsuoka ,  Atsushi Ike

IPC分类号： G06F9/44

CPC分类号： G06F11/3457 ,  G06F9/524 ,  G06F11/3632 ,  G06F11/3664

摘要： A method of simulating software by use of a computer includes executing a program inclusive of a plurality of threads by a hardware model implemented as software on a software simulator, utilizing a monitor function of the simulator to collect information about accesses by monitoring accesses made by the plurality of threads with respect to resources provided in the hardware model, utilizing the monitor function to detect, from the collected information, overlapping accesses made to an identical resource area by two or more of the threads, and utilizing the monitor function to generate a message for warning of the overlapping accesses.

摘要翻译： 通过使用计算机来模拟软件的方法包括通过在软件模拟器上作为软件实现的硬件模型执行包括多个线程的程序，利用模拟器的监视功能来通过监视由 多个线程相对于在硬件模型中提供的资源，利用监视功能从所收集的信息中检测由两个或多个线程对相同资源区域进行的重叠访问，并利用监视功能来生成消息 用于警告重叠访问。

公开(公告)号：US20070101318A1

公开(公告)日：2007-05-03

申请号：US11362828

申请日：2006-02-28

申请人： Masato Tatsuoka ,  Atsushi Ike

发明人： Masato Tatsuoka ,  Atsushi Ike

IPC分类号： G06F9/44

CPC分类号： G06F17/5022 ,  G06F9/52 ,  G06F2217/86

摘要： Core model processing of a processor model PE1 and a processor model PE2 is serialized. Therefore, processing time for the inter-core-model communication is required between the core model processing of a first processor model and the core model processing of a second processor model. The inter-core-model communication processing is performed such that the inter-core-model communication required for the simulation processing of a multi-processor model is performed in parallel with the core model processing.

摘要翻译： 将处理器型号PE 1和处理器型号PE 2的核心模型处理序列化。 因此，在第一处理器模型的核心模型处理和第二处理器模型的核心模型处理之间需要用于核心间模型通信的处理时间。 执行核心间模型通信处理，使得与核心模型处理并行执行多处理器模型的模拟处理所需的核心间模型通信。

公开(公告)号：US08725485B2

公开(公告)日：2014-05-13

申请号：US12037297

申请日：2008-02-26

申请人： Masato Tatsuoka ,  Atsushi Ike

发明人： Masato Tatsuoka ,  Atsushi Ike

IPC分类号： G06F17/50

CPC分类号： G06F11/36

摘要： A simulation method and apparatus including a restore point setting unit setting restore points in core models for executing threads using parallel processing. The method also includes storing information for reproducing a state the core models at the restore points.

摘要翻译： 一种仿真方法和装置，包括恢复点设置单元，用于在使用并行处理执行线程的核心模型中设置恢复点。 该方法还包括存储用于在还原点再现核心模型的状态的信息。

公开(公告)号：US07873507B2

公开(公告)日：2011-01-18

申请号：US11235227

申请日：2005-09-27

申请人： Masato Tatsuoka ,  Atsushi Ike

发明人： Masato Tatsuoka ,  Atsushi Ike

IPC分类号： G06F9/44 ,  G06F17/50 ,  G06F13/10 ,  G06F13/12 ,  G06F9/45

CPC分类号： G06F11/261 ,  G06F9/52 ,  G06F9/522

摘要： A high-speed multicore model simulator is realized. A multicore model simulator having a plurality of threads, and a plurality of core models executing the aforesaid plurality of threads is provided. The plurality of core models are a plurality of processor core models, each of which executes one thread, and they are synchronized with each other every predetermined number of execution instructions of each thread.

摘要翻译： 实现了高速多核模拟器。 提供具有多个线程的多核模型模拟器和执行上述多个线程的多个核心模型。 多个核心模型是多个处理器核心模型，每个处理器核心模型执行一个线程，并且每个线程的预定数量的执行指令彼此同步。