公开(公告)号：US09384156B2

公开(公告)日：2016-07-05

申请号：US14086860

申请日：2013-11-21

申请人： MICROSOFT TECHNOLOGY LICENSING, LLC

发明人： Nhon Quach ,  Stephen Z. Au ,  Thomas Zou ,  Tracy Sharpe

IPC分类号： G06F13/24 ,  G06F13/28 ,  G06F13/32 ,  G06F13/38 ,  G06F13/40

CPC分类号： G06F13/32 ,  G06F13/24 ,  G06F13/28 ,  G06F13/385 ,  G06F13/4027 ,  G06F2213/0026 ,  G06F2213/0038

摘要： One disclosed computing system comprises a x86 processor, memory, a PCIe root complex (RC), a PCIe bus, and an interconnect chip having a PCIe endpoint (EP) that is connected to the PCIe RC through a PCIe link, the PCIe EP being connected to an AMBA® bus. The interconnect chip may communicate with the IO device via the AMBA® bus in an AMBA® compliant manner and communicate with the host system in a PCIe compliant manner. This communication may include receiving a command from the processor, sending the command to the IO device over the AMBA® bus, receiving a response from the IO device over the AMBA® bus, and sending over the AMBA® bus and the PCIe link one or more DMA operations to the memory. Further communication may include sending an IOAPIC interrupt to the processor of the host system according to PCIe ordering rules.

摘要翻译： 一种公开的计算系统包括x86处理器，存储器，PCIe根复合（RC），PCIe总线和具有通过PCIe链路连接到PCIe RC的PCIe端点（EP）的互连芯片，PCIe EP 连接到AMBA®总线。 互连芯片可以通过AMBA®总线以符合AMBA的方式与IO设备通信，并以PCIe兼容方式与主机系统进行通信。 该通信可以包括从处理器接收命令，通过AMBA总线将命令发送到IO设备，通过AMBA总线接收来自IO设备的响应，以及通过AMBA®总线和PCIe链路发送一个或 更多的DMA操作到内存。 进一步的通信可以包括根据PCIe排序规则向主机系统的处理器发送IOAPIC中断。