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公开(公告)号：US09563369B2
公开(公告)日：2017-02-07
申请号：US14252673
申请日：2014-04-14
发明人： Nhon Toai Quach , Susan Carrie , Jeffrey Andrews , John Sell , Kevin Po
CPC分类号： G06F3/0613 , G06F3/0631 , G06F3/0674 , G06F13/1605 , G06F13/1626 , G06F13/1642 , G06F13/1668
摘要： Systems and methods for applying a fine-grained QoS logic are provided. The system may include a memory controller, the memory controller configured to receive memory access requests from a plurality of masters via a bus fabric. The memory controller determines the priority class of each of the plurality of masters, and further determines the amount of memory data bus bandwidth consumed by each master on the memory data bus. Based on the priority class assigned to each of the masters and the amount of memory data bus bandwidth consumed by each master, the memory controller applies a fine-grained QoS logic to compute a schedule for the memory requests. Based on this schedule, the memory controller converts the memory requests to memory commands, sends the memory commands to a memory device via a memory command bus, and receives a response from the memory device via a memory data bus.
摘要翻译： 提供了应用细粒度的QoS逻辑的系统和方法。 该系统可以包括存储器控制器，该存储器控制器经配置以经由总线结构从多个主器件接收存储器访问请求。 存储器控制器确定多个主器件中的每一个的优先等级，并进一步确定存储器数据总线上每个主器件消耗的存储器数据总线带宽的量。 基于分配给每个主器件的优先级等级和每个主器件消耗的存储器数据总线带宽的数量，存储器控制器应用细粒度的QoS逻辑来计算存储器请求的调度。 基于该时间表，存储器控制器将存储器请求转换为存储器命令，通过存储器命令总线将存储器命令发送到存储器设备，并且经由存储器数据总线从存储器设备接收响应。
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公开(公告)号：US09424490B2
公开(公告)日：2016-08-23
申请号：US14318135
申请日：2014-06-27
发明人： Adam James Muff , John Allen Tardif , Susan Carrie , Mark J. Finocchio , Kyungsuk David Lee , Christopher Douglas Edmonds , Randy Crane
CPC分类号： G06K9/6267 , G06K9/00973 , G06K9/6282
摘要： Embodiments are disclosed that relate to processing image pixels. For example, one disclosed embodiment provides a system for classifying pixels comprising retrieval logic; a pixel storage allocation including a plurality of pixel slots, each pixel slot being associated individually with a pixel, where the retrieval logic is configured to cause the pixels to be allocated into the pixel slots in an input sequence; pipelined processing logic configured to output, for each of the pixels, classification information associated with the pixel; and scheduling logic configured to control dispatches from the pixel slots to the pipelined processing logic, where the scheduling logic and pipelined processing logic are configured to act in concert to generate the classification information for the pixels in an output sequence that differs from and is independent of the input sequence.
摘要翻译： 公开了涉及处理图像像素的实施例。 例如，一个公开的实施例提供了一种用于对包括检索逻辑的像素进行分类的系统; 包括多个像素时隙的像素存储分配，每个像素时隙与像素相关联，其中所述检索逻辑被配置为使所述像素被分配到输入序列中的所述像素时隙中; 流水线处理逻辑被配置为针对每个像素输出与像素相关联的分类信息; 以及调度逻辑，被配置为控制从像素时隙到流水线处理逻辑的调度，其中调度逻辑和流水线处理逻辑被配置为一致地起作用以产生与输出序列不同且独立于的输出序列中的像素的分类信息 输入序列。
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