公开(公告)号：US20220269487A1

公开(公告)日：2022-08-25

申请号：US17180993

申请日：2021-02-22

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Adir Zevulun ,  Uria Basher ,  Nir Shmuel ,  Ben Witulski

IPC: G06F7/72 ,  G06F21/60

Abstract: An Integrated Montgomery Calculation Engine (IMCE), for multiplying two multiplicands modulo a predefined number, includes a Carry Save Adder (CSA) circuit and control circuitry. The CSA circuit has multiple inputs, and has outputs including a sum output and a carry output. The control circuitry is coupled to the inputs and the outputs of the CSA circuit and is configured to operate the CSA circuit in at least (i) a first setting that calculates a Montgomery precompute value and (ii) a second setting that calculates a Montgomery multiplication of the two multiplicands.

公开(公告)号：US12131132B2

公开(公告)日：2024-10-29

申请号：US17180993

申请日：2021-02-22

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Adir Zevulun ,  Uria Basher ,  Nir Shmuel ,  Ben Witulski

IPC: G06F7/72

CPC classification number: G06F7/728

Abstract: An Integrated Montgomery Calculation Engine (IMCE), for multiplying two multiplicands modulo a predefined number, includes a Carry Save Adder (CSA) circuit and control circuitry. The CSA circuit has multiple inputs, and has outputs including a sum output and a carry output. The control circuitry is coupled to the inputs and the outputs of the CSA circuit and is configured to operate the CSA circuit in at least (i) a first setting that calculates a Montgomery precompute value and (ii) a second setting that calculates a Montgomery multiplication of the two multiplicands.

公开(公告)号：US12079594B2

公开(公告)日：2024-09-03

申请号：US17180999

申请日：2021-02-22

Applicant: Mellanox Technologies, Ltd.

Inventor： Adir Zevulun ,  Uria Basher ,  Nir Shmuel ,  Ben Witulski

IPC: G06F7/72 ,  G06F21/60

CPC classification number: G06F7/728 ,  G06F21/602

Abstract: A Montgomery multiplication apparatus (MMA), for multiplying two multiplicands modulo a predefined number, includes a pre-compute circuit and a Montgomery multiplication circuit. The pre-compute circuit is configured to compute a Montgomery pre-compute value by performing a series of iterations. In a given iteration, the pre-compute circuit is configured to modify one or more intermediate values by performing bit-wise operations on the intermediate values calculated in a preceding iteration. The Montgomery multiplication circuit is configured to multiply the two multiplicands, modulo the predefined number, by performing a plurality of Montgomery reduction operations using the Montgomery pre-compute value computed by the pre-compute circuit.

公开(公告)号：US20220269488A1

公开(公告)日：2022-08-25

申请号：US17180999

申请日：2021-02-22

Applicant: Mellanox Technologies, Ltd.

Inventor： Adir Zevulun ,  Uria Basher ,  Nir Shmuel ,  Ben Witulski

IPC: G06F7/72 ,  G06F21/60

Abstract: A Montgomery multiplication apparatus (MMA), for multiplying two multiplicands modulo a predefined number, includes a pre-compute circuit and a Montgomery multiplication circuit. The pre-compute circuit is configured to compute a Montgomery pre-compute value by performing a series of iterations. In a given iteration, the pre-compute circuit is configured to modify one or more intermediate values by performing bit-wise operations on the intermediate values calculated in a preceding iteration. The Montgomery multiplication circuit is configured to multiply the two multiplicands, modulo the predefined number, by performing a plurality of Montgomery reduction operations using the Montgomery pre-compute value computed by the pre-compute circuit.

公开(公告)号：US10171103B1

公开(公告)日：2019-01-01

申请号：US15870161

申请日：2018-01-12

Applicant: Mellanox Technologies Ltd.

Inventor： Adir Zevulun ,  Noam Rom ,  Nir Shmuel

IPC: H03M7/34 ,  H03M7/30 ,  H03M7/40

Abstract: A hardware compression architecture including a shift register including: a plurality of sequentially coupled stages and a window stage coupled at an output end of the shift register, the shift register configured to receive an uncompressed data stream at an input end and output the uncompressed data from the window stage; a plurality of comparators each coupled to receive a data value held in a corresponding stage of the shift register and a data value held in the window stage, each of the comparators being configured to output a comparison result indicating whether the received stage value and the window stage data value match; logic, coupled to the comparators to receive the comparison results, to selectively compute one or more indexes based on the comparisons; and an encoder coupled to receive the one or more indexes and output, based on the one or more indexes, a position of a matching data value and a length of a matching sequence of data values.