公开(公告)号：US20190288672A1

公开(公告)日：2019-09-19

申请号：US16157165

申请日：2018-10-11

Applicant: MEDIATEK Inc.

Inventor： Tien-Yu LO ,  Chan-Hsiang WENG ,  Patrick Cooney ,  Tsung-Kai KAO ,  Stacy HO

IPC: H03H17/04

Abstract: The invention provides an anti-aliasing filter (AAF) for discretization at a sampling period. The AAF may include an operational amplifier having an input terminal and an output terminal, a first capacitor coupled between the input terminal and the output terminal, a second capacitor, and a first switch coupled between the first capacitor and the second capacitor. During a first phase, the first switch may conduct the second capacitor to the first capacitor. During a second phase, the first switch may stop conducting the second capacitor to the first capacitor. The first phase may last for one said sampling period.

公开(公告)号：US20190288705A1

公开(公告)日：2019-09-19

申请号：US16151404

申请日：2018-10-04

Applicant: MEDIATEK Inc.

Inventor： Tien-Yu LO

IPC: H03M3/00

Abstract: A delta-sigma modulator comprising: a first loop filter for filtering a first signal to a second signal, a second loop filter for filtering a third signal, a comparator, a register coupled to the comparator, a first capacitor bank and a second capacitor bank parallelly coupled between the second loop filter and the comparator, a first path causing a delayed signal to be linearly combined with an input signal to form the first signal, and a second path causing the delayed signal to be linearly combined with the second signal to form the third signal, wherein the delayed signal may be formed by delaying an output signal of the register.

公开(公告)号：US20160211856A1

公开(公告)日：2016-07-21

申请号：US14938567

申请日：2015-11-11

Applicant: Mediatek Inc.

Inventor： Khurram MUHAMMAD ,  Chi-Lun LO ,  Frank OP 'T EYNDE ,  Michael A. ASHBURN, JR. ,  Tien-Yu LO

IPC: H03M1/06 ,  H03M1/12

CPC classification number: H03M1/0626 ,  H03M1/1255 ,  H03M1/60

Abstract: A method and apparatus for a digitally-corrected analog-to-digital converter (ADC) are disclosed. The apparatus comprises a nonlinearity generator that generates one or more nonlinear characteristics of a time varying input signal and that causes unwanted signal components at frequencies other than a frequency of the time varying input signal, a frequency modifier coupled to the nonlinearity generator that modifies the unwanted signal components by altering an amplitude of the unwanted signal components, a frequency compensator coupled to the frequency modifier, wherein the frequency compensator compensates for the modification introduced by the frequency modifier to provide a filtered digital signal, and an inverse nonlinearity generator coupled to the frequency compensator for receiving the filtered digital signal, wherein the inverse nonlinearity generator compensates for the one or more nonlinear characteristics.

Abstract translation: 公开了一种用于数字校正的模拟 - 数字转换器（ADC）的方法和装置。 该装置包括非线性发生器，其产生时变输入信号的一个或多个非线性特性，并且在不同于时变输入信号的频率的频率下产生不想要的信号分量，耦合到非线性发生器的频率修改器修改不需要的 通过改变不需要的信号分量的幅度的信号分量，耦合到频率修改器的频率补偿器，其中频率补偿器补偿由频率修改器引入的修改以提供经滤波的数字信号，以及耦合到频率的逆非线性发生器 补偿器，用于接收经滤波的数字信号，其中逆非线性发生器补偿一个或多个非线性特性。