公开(公告)号：US20250080128A1

公开(公告)日：2025-03-06

申请号：US18822479

申请日：2024-09-03

Applicant: MEDIATEK INC.

Inventor： SUJITH KUMAR BILLA ,  Sung-Han Wen

IPC: H03M1/08

Abstract: A DAC cell circuit includes: at least a DAC cell, including: a first MOSFET having a drain coupled to a first switch for receiving a first current and coupled to a second switch for generating a second current, a source coupled to ground, and a gate coupled to a first bias voltage; a capacitor coupled between the gate and the drain of the first MOSFET; and a dead-band switch coupled between the gate of the first MOSFET and the bias node. The dead-band switch is controlled by a signal which is periodic with respect to a frequency equal to an input data rate of the DAC cell, and the dead-band switch is open during a data transition.