公开(公告)号：US20230299449A1

公开(公告)日：2023-09-21

申请号：US18079847

申请日：2022-12-12

Applicant: MEDIATEK INC.

Inventor： Li Gao ,  Zhiming Deng

IPC: H01P1/00

CPC classification number: H01P1/00

Abstract: An electronic device and a method for reducing power consumption of signal transmission in the electronic device are provided. The electronic device may include a source circuit, a destination circuit, at least one transmission wire and at least one resonance wire, wherein the at least one transmission wire is coupled between at least one output terminal of the source circuit and at least one input terminal of the destination circuit, and the at least one resonance wire is coupled to the at least one input terminal of the destination circuit and is routed along the at least one transmission wire. In specific, the source circuit is configured to output an oscillation signal having an oscillation frequency, the destination circuit is configured to receive the oscillation signal, wherein the at least one transmission wire is configured to transmit the oscillation signal from the source circuit to the destination circuit.

公开(公告)号：US11996598B2

公开(公告)日：2024-05-28

申请号：US18079847

申请日：2022-12-12

Applicant: MEDIATEK INC.

Inventor： Li Gao ,  Zhiming Deng

IPC: H01P1/00

CPC classification number: H01P1/00

Abstract: An electronic device and a method for reducing power consumption of signal transmission in the electronic device are provided. The electronic device may include a source circuit, a destination circuit, at least one transmission wire and at least one resonance wire, wherein the at least one transmission wire is coupled between at least one output terminal of the source circuit and at least one input terminal of the destination circuit, and the at least one resonance wire is coupled to the at least one input terminal of the destination circuit and is routed along the at least one transmission wire. In specific, the source circuit is configured to output an oscillation signal having an oscillation frequency, the destination circuit is configured to receive the oscillation signal, wherein the at least one transmission wire is configured to transmit the oscillation signal from the source circuit to the destination circuit.

公开(公告)号：US20230412136A1

公开(公告)日：2023-12-21

申请号：US18086600

申请日：2022-12-21

Applicant: MEDIATEK INC.

Inventor： Zhiming Deng ,  Qian Zhong ,  Li Gao

IPC: H03G5/16 ,  H03G3/30

CPC classification number: H03G5/165 ,  H03G3/30 ,  H03G2201/103

Abstract: A gain equalizer and a method for controlling a tunable gain of the gain equalizer are provided. The gain equalizer includes a common source stage and a switch array. The common source stage is configured to apply the tunable gain to an input signal, in order to generate an amplified signal. The common source stage includes input transistors and cascode transistors, wherein the cascode transistors are respectively coupled to the input transistors. The input transistors are configured to receive the input signal via gate terminals of the input transistors, respectively, and the cascode transistors are configured to output the amplified signal via drain terminals of the cascode transistors, respectively. In addition, the switch array is coupled between respective source terminals of the cascode transistors, wherein the tunable gain is controlled according to an equivalent impedance of the switch array.

公开(公告)号：US20230318556A1

公开(公告)日：2023-10-05

申请号：US18122693

申请日：2023-03-16

Applicant: MEDIATEK INC.

Inventor： Zhiming Deng ,  Li Gao

IPC: H03G3/30 ,  H03F3/217 ,  H03F1/02

CPC classification number: H03G3/3026 ,  H03F3/2178 ,  H03F1/0244 ,  H03F2200/294

Abstract: A variable gain low noise amplifier (LNA) and a method for controlling a gain of the variable gain LNA are provided. The variable gain LNA may include a first transistor, a first degeneration inductor, a second transistor and a second degeneration inductor, wherein the first degeneration inductor is coupled to a source terminal of the first transistor, and the second degeneration inductor is coupled to a source terminal of the second transistor. Gate terminals of the first transistor and the second transistor are configured to receive an input signal. The first transistor and the first degeneration inductor belong to a first branch of the variable gain LNA, and the second transistor and the second degeneration inductor belong to a second branch of the variable gain LNA. More particularly, a gain of the variable gain LNA is determined by controlling whether to turn off the second branch.