RESOLVER INTERFACE AND SIGNAL CONDITIONER
    1.
    发明申请
    RESOLVER INTERFACE AND SIGNAL CONDITIONER 有权
    解决方案界面和信号调节器

    公开(公告)号:US20100097052A1

    公开(公告)日:2010-04-22

    申请号:US12252603

    申请日:2008-10-16

    IPC分类号: G01B7/30

    摘要: A resolver interface includes separate anti-aliasing filters for sine and cosine signals. The separately filtered signals are then time share multiplexed to a single analog to digital (A/D) converter. Because all of the inputs are fed through the same A/D converter, any error, difference or shift caused by the A/D converter is shared across al of the inputs. A Field Programmable Gate Array (FPGA) and processor are used to digitally filter, demodulate and compute position.

    摘要翻译: 解析器接口包括用于正弦和余弦信号的单独抗混叠滤波器。 然后将单独滤波的信号与单个模数(A / D)转换器进行时分复用。 因为所有的输入都是通过相同的A / D转换器馈电的,所以A / D转换器引起的任何误差,差值或偏移都是由输入端共享的。 现场可编程门阵列(FPGA)和处理器用于数字滤波,解调和计算位置。

    Resolver interface and signal conditioner
    2.
    发明授权
    Resolver interface and signal conditioner 有权
    旋转变压器接口和信号调节器

    公开(公告)号:US07977936B2

    公开(公告)日:2011-07-12

    申请号:US12252603

    申请日:2008-10-16

    IPC分类号: G01B7/30

    摘要: A resolver interface includes separate anti-aliasing filters for sine and cosine signals. The separately filtered signals are then time share multiplexed to a single analog to digital (A/D) converter. Because all of the inputs are fed through the same A/D converter, any error, difference or shift caused by the A/D converter is shared across al of the inputs. A Field Programmable Gate Array (FPGA) and processor are used to digitally filter, demodulate and compute position.

    摘要翻译: 解析器接口包括用于正弦和余弦信号的单独抗混叠滤波器。 然后将单独滤波的信号与单个模数(A / D)转换器进行时分复用。 因为所有的输入都是通过相同的A / D转换器馈电的,所以A / D转换器引起的任何误差,差值或偏移都是由输入端共享的。 现场可编程门阵列(FPGA)和处理器用于数字滤波,解调和计算位置。

    Load shedding circuit for RAM air turbines
    3.
    发明授权
    Load shedding circuit for RAM air turbines 有权
    RAM空气涡轮机负载脱落电路

    公开(公告)号:US09083201B2

    公开(公告)日:2015-07-14

    申请号:US13232199

    申请日:2011-09-14

    IPC分类号: H02J9/08 H02J9/06

    摘要: A power generation/distribution system includes a RAM air turbine (RAT) generator and an emergency integrated control center (EICC) that selectively applies either primary power provided by a primary power source or emergency power developed by the RAT generator to an alternating current essential bus (AC ESS bus) for distribution to one or more essential loads. The EICC monitors the primary power and in response to a loss of primary power selectively disables the supply of power from the AC ESS bus to the essential loads and manages subsequent loading of the RAT generator by the essential loads.

    摘要翻译: 发电/配电系统包括RAM空气涡轮机(RAT)发电机和紧急综合控制中心(EICC),其选择性地将由主电源提供的主电源或由RAT发电机开发的应急电源施加到交流电源必需总线 (AC ESS总线)分配到一个或多个基本负载。 EICC监控主要功率并响应于主功率的损失,选择性地禁止从AC ESS总线向主要负载供电,并管理基本负载的RAT发电机的后续负载。

    LOAD SHEDDING CIRCUIT FOR RAM AIR TURBINES
    4.
    发明申请
    LOAD SHEDDING CIRCUIT FOR RAM AIR TURBINES 有权
    用于RAM空气涡轮机的负载冲击电路

    公开(公告)号:US20130062943A1

    公开(公告)日:2013-03-14

    申请号:US13232199

    申请日:2011-09-14

    IPC分类号: H02J9/00

    摘要: A power generation/distribution system includes a RAM air turbine (RAT) generator and an emergency integrated control center (EICC) that selectively applies either primary power provided by a primary power source or emergency power developed by the RAT generator to an alternating current essential bus (AC ESS bus) for distribution to one or more essential loads. The EICC monitors the primary power and in response to a loss of primary power selectively disables the supply of power from the AC ESS bus to the essential loads and manages subsequent loading of the RAT generator by the essential loads.

    摘要翻译: 发电/配电系统包括RAM空气涡轮机(RAT)发电机和紧急综合控制中心(EICC),其选择性地将由主电源提供的主电源或由RAT发电机开发的应急电源施加到交流电源必需总线 (AC ESS总线)分配到一个或多个基本负载。 EICC监控主要功率并响应于主功率的损失,选择性地禁止从AC ESS总线向主要负载供电,并管理基本负载的RAT发电机的后续负载。