公开(公告)号：US5534786A

公开(公告)日：1996-07-09

申请号：US392428

申请日：1995-02-22

申请人： Kazuo Kaneko ,  Masayasu Katayama ,  Kiyoshi Kochi

发明人： Kazuo Kaneko ,  Masayasu Katayama ,  Kiyoshi Kochi

IPC分类号： G01R31/28

CPC分类号： G01R31/287 ,  G01R31/2831

摘要： Disclosed is an improved burn-in and test method of semiconductor wafers each having numerous integrated circuits formed therein. It includes the steps of dividing each semiconductor wafer into blocks each including some integrated circuits; giving each block an address to indicate in which part of the semiconductor wafer the integrated circuits of the block are placed; recording the addresses of all blocks; preparing burn-in boards each having sockets to detachably hold carriers each bearing an identification code; loading each carrier with a block to be tested; fitting each carrier in a selected socket in the burn-in board; and carrying out the burn-in and required tests on the blocks of each burn-in board. Analysis of test results permits the locating of defective integrated circuits, if any in semiconductor wafers in terms of the recorded addresses of the blocks and the identification codes of the carriers.

摘要翻译： 公开了一种在其中形成有许多集成电路的半导体晶片的改进的老化和测试方法。 它包括以下步骤：将每个半导体晶片分成包括一些集成电路的块; 给每个块指示在块的哪个部分放置块的集成电路的地址; 记录所有块的地址; 准备具有插座的老化板，以可拆卸地保持承载识别码的载体; 用要测试的块加载每个载体; 将每个载体安装在老化板中选定的插座中; 并对每个老化板的块进行老化和测试。 测试结果的分析允许根据块的记录地址和载波的识别码来定位有缺陷的集成电路（如果有的话）在半导体晶片中。