公开(公告)号：US09780787B2

公开(公告)日：2017-10-03

申请号：US14228522

申请日：2014-03-28

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Kwang Hyun Cho ,  I Saak Yang ,  Sung Hoon Jung

IPC: H03M13/03 ,  H03M13/00 ,  G11C29/00 ,  H03K19/003

CPC classification number: H03K19/003 ,  G11C29/76

Abstract: Provided is a fault self-repairing circuit sequentially converting an N-bit output value according to a pre-determined schedule and outputting the converted result. The fault self-repairing circuit includes different N logic modules configured to output each bit of the N bits. Here, each of the logic modules includes an internal logic. When the N-bit output value is identical to a pre-determined value, an output value of each of the logic modules is provided by the internal logic, and, when the N-bit output value is not identical to the pre-determined value, the output value of each of the logic modules is provided with a correct value provided outside each of the logic modules.

公开(公告)号：US20140298143A1

公开(公告)日：2014-10-02

申请号：US14228522

申请日：2014-03-28

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Kwang Hyun Cho ,  I Saak Yang ,  Sung Hoon Jung

IPC: H03M13/03

CPC classification number: H03K19/003 ,  G11C29/76

Abstract: Provided is a fault self-repairing circuit sequentially converting an N-bit output value according to a pre-determined schedule and outputting the converted result. The fault self-repairing circuit includes different N logic modules configured to output each bit of the N bits. Here, each of the logic modules includes an internal logic. When the N-bit output value is identical to a pre-determined value, an output value of each of the logic modules is provided by the internal logic, and, when the N-bit output value is not identical to the pre-determined value, the output value of each of the logic modules is provided with a correct value provided outside each of the logic modules.

Abstract translation: 提供了一种故障自修复电路，其根据预定时间顺序地转换N位输出值并输出转换结果。 故障自修复电路包括配置为输出N位的每个位的不同N个逻辑模块。 这里，每个逻辑模块包括内部逻辑。 当N位输出值与预定值相同时，每个逻辑模块的输出值由内部逻辑提供，并且当N位输出值与预定值不相同时 每个逻辑模块的输出值被提供有在每个逻辑模块之外提供的正确值。

公开(公告)号：US10008198B2

公开(公告)日：2018-06-26

申请号：US14143068

申请日：2013-12-30

Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Kwang-Hyun Cho ,  Byeongwook Lee ,  Sung Hoon Jung

IPC: G10L15/00 ,  G10L21/00 ,  G10L17/00 ,  G10L21/02 ,  G06F17/30 ,  G10L15/04

CPC classification number: G10L15/04

Abstract: A method of segmenting input speech signal into plurality of frames for speech recognition is disclosed. The method includes extracting a low frequency signal from the speech signal, and segmenting the speech signal into a plurality of time-intervals according to a plurality of instantaneous phase-sections of the low frequency signal.