公开(公告)号：US20210034957A1

公开(公告)日：2021-02-04

申请号：US16922333

申请日：2020-07-07

Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Minsoo RHU ,  Youngeun KWON ,  YunJae LEE

IPC: G06N3/063 ,  G06F9/50 ,  G06K9/62 ,  G06F17/16

Abstract: Disclosed are a neural network acceleration system and an operating method of the same. The neural network acceleration system includes a first memory module that generates a first reduced embedding segment through a tensor operation, based on a first segment of a first embedding and a second segment of a second embedding, a second memory module that generates a second reduced embedding segment through the tensor operation, based on a third segment of the first embedding and a fourth segment of the second embedding, and a processor that processes a reduced embedding including the first reduced embedding segment and the second reduced embedding segment, based on a neural network algorithm.

公开(公告)号：US20210256373A1

公开(公告)日：2021-08-19

申请号：US17119197

申请日：2020-12-11

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Jaehyung AHN ,  Minsoo RHU ,  Yujeong CHOI

IPC: G06N3/08 ,  G06N3/04 ,  G06N3/063

Abstract: A method of operating the accelerator includes receiving a request for preemption during an execution of a first task using one or more processing elements included in the accelerator, in response to the request for preemption, moving context information of the first task stored in an internal memory of the accelerator to an external memory of the accelerator, and executing a second task associated with the request for preemption using the processing elements.

公开(公告)号：US20240012690A1

公开(公告)日：2024-01-11

申请号：US18348667

申请日：2023-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  Korea Advanced Institute of Science and Technology

Inventor： Minsoo RHU ,  Yunseong KIM ,  Yujeong CHOI

IPC: G06F9/50 ,  G06F9/48

CPC classification number: G06F9/5061 ,  G06F9/5027 ,  G06F9/4881 ,  G06F2209/503 ,  G06F2209/5022

Abstract: An electronic device and method for partitioning an accelerator and scheduling batches are disclosed. An electronic device includes one or more processors, and a memory storing instructions configured to cause the one or more processors to, for a first partitioning of an accelerator into partitions of different sizes, based on resource utilization of the partitions batch of different sizes input to the partition, determine correspondences between the sizes of the batches and the sizes of the partitions in the first partitioning, determine numbers of partitions for the respective determined sizes of the partitions based on the correspondences between the sizes of the batches and the sizes of the partitions in the first partitioning, and partition the accelerator into a second partitioning based on the determined numbers of the respective sizes of the partitions.