公开(公告)号：US20250069994A1

公开(公告)日：2025-02-27

申请号：US18945469

申请日：2024-11-12

Applicant: KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA MATERIALS CO., LTD.

Inventor： Akito SASAKI ,  Kentaro IWAI ,  Keita KANAHARA

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/498 ,  H01L29/34

Abstract: A ceramic circuit substrate according to an embodiment includes a ceramic substrate and multiple metal parts. The ceramic substrate includes a first surface. The multiple metal parts are located respectively in multiple first regions of the first surface. The first surface includes a second region positioned between adjacent first regions of the multiple metal parts. An average length RSm of roughness curve elements in the second region is not less than 40 μm. The average length RSm is preferably not more than 100 μm. A maximum peak height Rp of a surface roughness curve in the second region is preferably not less than 1.0 μm. A maximum valley depth Rv of a surface roughness curve in the second region is preferably not less than 1.0 μm.