公开(公告)号：US09817773B2

公开(公告)日：2017-11-14

申请号：US14870683

申请日：2015-09-30

Applicant: JUNIPER NETWORKS, INC.

Inventor： Raymond Marcelino Manese Lim ,  Stefan Dyckerhoff ,  Jeffrey Glenn Libby ,  Teshager Tesfaye

IPC: G06F9/455 ,  G06F13/16 ,  G06F12/00 ,  H04L12/721 ,  H04L12/861 ,  G06F9/48 ,  G06F13/40

CPC classification number: G06F13/1626 ,  G06F9/4881 ,  G06F12/00 ,  G06F13/1663 ,  G06F13/4022 ,  H04L45/62 ,  H04L49/90 ,  H04L49/9094

Abstract: A device includes an input processing unit and an output processing unit. The input processing unit dispatches first data to one of a group of processing engines, records an identity of the one processing engine in a location in a first memory, reserves one or more corresponding locations in a second memory, causes the first data to be processed by the one processing engine, and stores the processed first data in one of the locations in the second memory. The output processing unit receives second data, assigns an entry address corresponding to a location in an output memory to the second data, transfers the second data and the entry address to one of a group of second processing engines, causes the second data to be processed by the second processing engine, and stores the processed second data to the location in the output memory.

公开(公告)号：US09178840B2

公开(公告)日：2015-11-03

申请号：US13774703

申请日：2013-02-22

Applicant: JUNIPER NETWORKS, INC.

Inventor： Raymond Marcelino Manese Lim ,  Stefan Dyckerhoff ,  Jeffrey Glenn Libby ,  Teshager Tesfaye

IPC: G06F9/46 ,  H04L12/28 ,  G06F13/00 ,  H04L12/861 ,  G06F12/00 ,  H04L12/721

CPC classification number: G06F13/1626 ,  G06F9/4881 ,  G06F12/00 ,  G06F13/1663 ,  G06F13/4022 ,  H04L45/62 ,  H04L49/90 ,  H04L49/9094

Abstract: A device includes an input processing unit and an output processing unit. The input processing unit dispatches first data to one of a group of processing engines, records an identity of the one processing engine in a location in a first memory, reserves one or more corresponding locations in a second memory, causes the first data to be processed by the one processing engine, and stores the processed first data in one of the locations in the second memory. The output processing unit receives second data, assigns an entry address corresponding to a location in an output memory to the second data, transfers the second data and the entry address to one of a group of second processing engines, causes the second data to be processed by the second processing engine, and stores the processed second data to the location in the output memory.

Abstract translation: 一种装置包括输入处理单元和输出处理单元。 输入处理单元将第一数据分配到一组处理引擎中的一个，将一个处理引擎的标识记录在第一存储器中的位置中，在第二存储器中保留一个或多个对应位置，使得第一数据被处理 并且将经处理的第一数据存储在第二存储器中的一个位置中。 输出处理单元接收第二数据，将对应于输出存储器中的位置的入口地址分配给第二数据，将第二数据和入口地址传送给一组第二处理引擎，使得第二数据被处理 并且将处理的第二数据存储到输出存储器中的位置。

公开(公告)号：US08811391B2

公开(公告)日：2014-08-19

申请号：US13684866

申请日：2012-11-26

Applicant: Juniper Networks, Inc.

Inventor： Philippe Lacroute ,  Matthew A. Tucker ,  John D. Weisbloom ,  Anjan Venkatramani ,  Jayabharat Boddu ,  Stefan Dyckerhoff

IPC: H04L12/50

CPC classification number: H04L49/10 ,  H04L49/15 ,  H04L49/1507 ,  H04L49/30 ,  H04L49/3027

Abstract: A switching device includes multiple interfaces and a switch fabric. The switch fabric includes switch integrated circuits arranged in a number of stages. Multiple virtual switch planes may be implemented in the switch fabric. Data traffic received at the interfaces is selectively assigned to different ones of the virtual switch planes.

Abstract translation: 交换设备包括多个接口和交换结构。 交换结构包括以多个级布置的开关集成电路。 可以在交换结构中实现多个虚拟交换机平面。 在接口处接收到的数据流量被选择性地分配给虚拟交换机的不同的平面。

公开(公告)号：US20130166856A1

公开(公告)日：2013-06-27

申请号：US13774703

申请日：2013-02-22

Applicant: JUNIPER NETWORKS, INC.

Inventor： Raymond Marcelino Manese LIM ,  Stefan Dyckerhoff ,  Jeffrey Glenn Libby ,  Teshager Tesfaye

IPC: G06F12/00

CPC classification number: G06F13/1626 ,  G06F9/4881 ,  G06F12/00 ,  G06F13/1663 ,  G06F13/4022 ,  H04L45/62 ,  H04L49/90 ,  H04L49/9094

Abstract: A device includes an input processing unit and an output processing unit. The input processing unit dispatches first data to one of a group of processing engines, records an identity of the one processing engine in a location in a first memory, reserves one or more corresponding locations in a second memory, causes the first data to be processed by the one processing engine, and stores the processed first data in one of the locations in the second memory. The output processing unit receives second data, assigns an entry address corresponding to a location in an output memory to the second data, transfers the second data and the entry address to one of a group of second processing engines, causes the second data to be processed by the second processing engine, and stores the processed second data to the location in the output memory.

Abstract translation: 一种装置包括输入处理单元和输出处理单元。 输入处理单元将第一数据分配到一组处理引擎中的一个，将一个处理引擎的标识记录在第一存储器中的位置中，在第二存储器中保留一个或多个对应位置，使得第一数据被处理 并且将经处理的第一数据存储在第二存储器中的一个位置中。 输出处理单元接收第二数据，将对应于输出存储器中的位置的入口地址分配给第二数据，将第二数据和入口地址传送给一组第二处理引擎，使得第二数据被处理 并且将处理的第二数据存储到输出存储器中的位置。