公开(公告)号：US09258192B2

公开(公告)日：2016-02-09

申请号：US14146981

申请日：2014-01-03

Applicant: Juniper Networks, Inc.

Inventor： Philip A. Thomas ,  Anurag Agrawal

IPC: H04L12/28 ,  H04L12/24

CPC classification number: H04L41/12 ,  H04L41/0876

Abstract: A multi-chassis network device may automatically detect whether cables connected between chassis devices are correctly inserted. The device may insert, into a first data stream output from a first port of the device, control information identifying the first port. The device may receive, from a second data stream received by the first port of the device, second control information identifying a second port, at another device connected to the device via a cable. The device may determine, based on the second control information, whether the connection of the first port to the second port, via the cable, is valid and cause, when the connection of the first port to the second port is determined to not be valid, the device to output an indication that the connection is not valid or to reconfigure the device to make the connection of the first port to the second port valid.

Abstract translation: 多机箱网络设备可以自动检测连接在机箱设备之间的电缆是否正确插入。 设备可以将从第一端口输出的第一数据流插入到识别第一端口的控制信息中。 设备可以从设备的第一端口接收的第二数据流接收标识第二端口的第二控制信息，在经由电缆连接到设备的另一设备处。 设备可以基于第二控制信息确定第一端口到第二端口的连接是否经过电缆是有效的，并且当第一端口到第二端口的连接被确定为不是有效的时 ，用于输出连接无效的指示的设备或重新配置设备以使第一端口与第二端口的连接有效。

公开(公告)号：US09104345B2

公开(公告)日：2015-08-11

申请号：US14211805

申请日：2014-03-14

Applicant: Juniper Networks, Inc.

Inventor： Anurag Agrawal ,  Philip A. Thomas

IPC: G06F3/00 ,  G06F1/04 ,  G06F5/12

CPC classification number: G06F5/12 ,  G06F1/04

Abstract: First in, first out (FIFO) queues may be used to transfer data between a producer clock domain and a number of consumer clock domains. In one implementation, a control component for the FIFO queues may include a number of counters, corresponding to each of the consumer clock domains, each of the counters maintaining a count value relating to an amount of data read by the corresponding consumer clock domain. The control component may additionally include a credit deduction component coupled to the count values of the counters, the credit deduction component determining whether any of the count values is above a threshold, and in response to the determination that any of the count values is above the threshold, reducing the count value of each of the counters and issuing a write pulse signal to the producer clock domain, the write pulse signal causing the producer clock domain to perform a write operation to the FIFO queues.

Abstract translation: 首先，先出（FIFO）队列可以用于在生成器时钟域和多个消费者时钟域之间传送数据。 在一个实现中，用于FIFO队列的控制组件可以包括与每个消费者时钟域相对应的多个计数器，每个计数器保持与由相应的消费者时钟域读取的数据量相关的计数值。 控制部件还可以包括耦合到计数器的计数值的信用扣除部件，信用扣除部件确定任何计数值是否高于阈值，并且响应于确定任何计数值高于 阈值，减少每个计数器的计数值并向生成器时钟域发出写入脉冲信号，该写入脉冲信号使得生成器时钟域对FIFO队列执行写入操作。

公开(公告)号：US08713220B2

公开(公告)日：2014-04-29

申请号：US13732198

申请日：2012-12-31

Applicant: Juniper Networks, Inc.

Inventor： Anurag Agrawal ,  Philip A. Thomas

IPC: G06F3/00

CPC classification number: H04L47/522 ,  H04L49/9047 ,  H04L49/9089

Abstract: A network device includes a main storage memory and a queue handling component. The main storage memory includes multiple memory banks which store a plurality of packets for multiple output queues. The queue handling component controls write operations to the multiple memory banks and controls read operations from the multiple memory banks, where the read operations for at least one of the multiple output queues alternates sequentially between the each of the multiple memory banks, and where the read operations and the write operations occur during a same clock period on different ones of the multiple memory banks.

Abstract translation: 网络设备包括主存储存储器和队列处理组件。 主存储器包括存储用于多个输出队列的多个分组的多个存储体。 队列处理组件控制对多个存储体的写入操作并控制来自多个存储体的读取操作，其中多个输出队列中的至少一个的读取操作在多个存储器组中的每一个之间顺序地交替，并且读取 操作和写入操作在多个存储体中的不同存储体上的同一时钟周期内发生。