摘要:
A DC current regulator circuit comprises a first circuit node (32) which is operable to receive an external input voltage. A transistor (M1) has an input, a first leg and a second leg. The first leg of the transistor is isolated from the first circuit node (32). An amplifier (10) has an output connected to the input of the transistor (M1), a first amplifier input for receiving a reference voltage (VREF) and a second amplifier input connected to the first circuit node (32). A low-pass filter (33) connects between the output of the amplifier and the first circuit node (32). A current mirror (36) connects in series with the second leg of the transistor (M1) and has a first branch (38) for providing a regulated output current and a second branch (37) which connects to the first circuit node (32). The current regulator has reduced sensitivity to conducted EMI received at the first circuit node (32).
摘要:
A driver circuit suitable for outputting a signal onto an output line affected by conducted EMI, has a slope control circuit and an output circuit, (op-amp, Mo, M13 to M21). It can be used for driving a LIN network. The slope control circuit outputs a slope controlled version of the input signal to the output circuit, which (M6,M7) is arranged to reduce an amount of conducted EMI induced DC shift in the output circuit. This can involve clipping a feedback signal, and regulating an output stage of the op-amp to prevent the DC shift. Having a separate output circuit can help shield the slope control circuit from the EMI on the output line.
摘要:
A driver circuit suitable for outputting a signal onto an output line affected by conducted EMI, has a slope control circuit and an output circuit, (op-amp, Mo, M13 to M21). It can be used for driving a LIN network. The slope control circuit outputs a slope controlled version of the input signal to the output circuit, which (M6,M7) is arranged to reduce an amount of conducted EMI induced DC shift in the output circuit. This can involve clipping a feedback signal, and regulating an output stage of the op-amp to prevent the DC shift. Having a separate output circuit can help shield the slope control circuit from the EMI on the output line.
摘要:
Electronic circuit (F) including input terminals (IN1,IN2) and output terminals (OUT1, OUT2) between which a desired filter transfer function (F(s) )is realised by said electronic circuit when an input signal is applied between said input terminals (IN1,IN2) is characterised in that said electronic circuit (F) includes at least one first passive series element (Z1) having a first series impedance, a first terminal of which is coupled to one of said input terminals (IN1), a second terminal of which is coupled to one of said output terminals (OUT1), said electronic circuit further including an active circuit (G) coupled between said output terminals (OUT1,OUT2), and including a filter circuit (H) with a filter transfer function (H(s)) such that said desired filter transfer function (F(s)) is obtained.
摘要:
A telecommunication filter arrangement comprising two similar filter cells (T1, S1a, S1b, R1a, R1b; T2, S2a, S2b, R2a, R2b) coupled in cascade to provide a POTS/ADSL splitter. The filter arrangement further comprises at third filter cell (C3, R3, S3) coupled in-between the two other filter cells and comprising a cell capacitor (C3) series coupled with the parallel connection of a cell coil (S3) and a cell resistor (R3). A 3rd order filter is so provided and the filter arrangement behaves as known 5th order filter but with a fixed “switchable insertion loss circuit”. This filter arrangement is thereby cheap, simple and has a small size with respect to the known filter arrangements, while providing good performances. The single FIGURE is attached to the abstract.
摘要:
A telecommunication filter arrangement comprising two similar filter cells (T1, S1a, S1b, R1a, R1b; T2, S2a, S2b, R2a, R2b) coupled in cascade to provide a POTS/ADSL splitter. The filter arrangement further comprises at third filter cell (C3, R3, S3) coupled in-between the two other filter cells and comprising a cell capacitor (C3) series coupled with the parallel connection of a cell coil (S3) and a cell resistor (R3). A 3rd order filter is so provided and the filter arrangement behaves as known 5th order filter but with a fixed “switchable insertion loss circuit”. This filter arrangement is thereby cheap, simple and has a small size with respect to the known filter arrangements, while providing good performances.