公开(公告)号：US20030123524A1

公开(公告)日：2003-07-03

申请号：US10040994

申请日：2001-12-28

Applicant: InterDigital Technology Corporation

Inventor： Ryan Samuel Buchert ,  Chayil Timmerman ,  Peter Edward Becker ,  Muhammad Usman Fazili

IPC: H04K001/00

CPC classification number: H04B1/7093 ,  H04B2201/70707

Abstract: An apparatus and method for data processing particularly useful in combining convolutions of the spreading code, scrambling code and channel response in order to construct a system transmission coefficient matrix, while maintaining the same circuit size and execution time relative to performing each convolution separately. One register for processing real channel response values and a second register for processing imaginary channel response values, are used for moving channel responses through the convolution. In place of multipliers, an optimized minimum number of adders connected in a pyramid configuration are used to perform the necessary multiplication of the codes, for simplicity of construction. By including the channel code transformation from binary representation to complex representation as part of the overall method, unnecessary adders are eliminated from the apparatus.

Abstract translation: 一种用于数据处理的装置和方法，在组合扩展码，扰码和信道响应的卷积时特别有用，以构建系统传输系数矩阵，同时分别相对于执行每个卷积保持相同的电路大小和执行时间。 用于处理实际信道响应值的一个寄存器和用于处理虚信道响应值的第二寄存器用于通过卷积移动信道响应。 代替乘法器，为了简化构造，使用以金字塔配置连接的优化的最小加法器数量来执行代码的必要乘法。 通过将来自二进制表示的信道码变换作为整体方法的一部分进行复杂表示，从装置中消除不必要的加法器。

公开(公告)号：US20030123418A1

公开(公告)日：2003-07-03

申请号：US10034824

申请日：2001-12-27

Applicant: InterDigital Technology Corporation

Inventor： Ryan Samuel Buchert ,  Chayil Timmerman ,  Younglok Kim

IPC: H04J003/00

CPC classification number: G06F7/24 ,  H04J3/047

Abstract: An insertion sorter circuit and method are provided which are particularly useful for sorting channel response values of a communication signal. The sorter circuit includes a series of sorter elements which each have a register. The circuit is configured to cascade values downwardly when one register receives a greater value than it has stored, which value is not greater than the value stored in any upstream register. At the end of processing the values, the most significant values are stored in the registers, the sum of which are the channel power estimate. The channel noise variance is obtainable by applying a system dependent scaling factor to the sum of the least significant values processed.

Abstract translation: 提供了一种插入分拣机电路和方法，其特别用于对通信信号的通道响应值进行排序。 分拣机电路包括各自具有寄存器的一系列分拣机元件。 该电路被配置为当一个寄存器接收到比它存储的值更大的值时向下级联值，该值不大于存储在任何上游寄存器中的值。 在处理这些值的最后，最重要的值存储在寄存器中，其总和是信道功率估计。 通过将系统相关的缩放因子应用于所处理的最低有效值的和来获得信道噪声方差。