公开(公告)号：US10891240B2

公开(公告)日：2021-01-12

申请号：US16024802

申请日：2018-06-30

Applicant: Intel Corporation

Inventor： Suresh Mathew ,  Mitchell Diamond ,  Kermin E. Fleming, Jr.

IPC: G06F12/1027 ,  G06F3/06

Abstract: Systems, methods, and apparatuses relating to low latency communications in a configurable spatial accelerator are described. In one embodiment, a processor includes a spatial array of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, a plurality of request address file circuits coupled to the spatial array of processing elements and a cache memory, each request address file circuit of the plurality of request address file circuits to access data in the cache memory in response to a request for data access from the spatial array of processing elements, a plurality of translation lookaside buffers comprising a translation lookaside buffer in each of the plurality of request address file circuits to provide an output of a physical address for an input of a virtual address, and a function controller to receive an interrupt that includes a first field, that when set to a first value, causes a shootdown message to be broadcast to the plurality of translation lookaside buffers to cause a shootdown in the plurality of translation lookaside buffers.