公开(公告)号：US20240103878A1

公开(公告)日：2024-03-28

申请号：US17953184

申请日：2022-09-26

Applicant: Intel Corporation

Inventor： Jayesh Gaur ,  Sufiyan Syed ,  Adithya Ranganathan ,  Sreenivas Subramoney

IPC: G06F9/38

CPC classification number: G06F9/3861 ,  G06F9/3867 ,  G06F9/3806

Abstract: An example of an integrated circuit may include a first execution cluster, a second execution cluster that is one or more of narrower and shallower as compared to the first execution cluster, and circuitry to selectively steer instructions to the first execution cluster and the second execution cluster based on branch misprediction information. Other embodiments are disclosed and claimed.

公开(公告)号：US20230195456A1

公开(公告)日：2023-06-22

申请号：US17558978

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Sufiyan Syed ,  Roger Gramunt ,  Jayesh Gaur ,  Priyank Deshpande

IPC: G06F9/28 ,  G06F9/22 ,  G06F9/48 ,  G06F9/50

CPC classification number: G06F9/28 ,  G06F9/223 ,  G06F9/4806 ,  G06F9/5027 ,  G06F2209/5014

Abstract: In one embodiment, an apparatus includes: a plurality of execution circuits to execute and instruct micro-operations (μops), where a subset of the plurality of execution circuits are capable of execution of a fused μop; a fusion circuit coupled to at least the subset of the plurality of execution circuits, wherein the fusion circuit is to fuse at least some pairs of producer-consumer μops into fused μops; and a fusion throttle circuit coupled to the fusion circuit, wherein the fusion throttle circuit is to prevent a first μop from being fused with another μop based at least in part on historical information associated with the first μop. Other embodiments are described and claimed.