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公开(公告)号：US20240214022A1
公开(公告)日：2024-06-27
申请号：US18145860
申请日：2022-12-23
Applicant: Intel Corporation
Inventor： Vamshi Krishna AAGIRU , Santhosh AP , Praveen Kashyap Ananta BHAT , Arjun C , Shailendra Singh CHAUHAN , Sajal Kumar DAS , Walid EL HAJJ , Isha GARG , Sagar GUPTA , Mallari HANCHATE , Mythili HEGDE , Siva Prasad JANGILI GANGA , Satyajit Siddharay KAMAT , Noam KOGOS , Ronen KRONFELD , Adiel LANGER , Gil MEYUHAS , Padmesh MURUGAN LATHA , Vishram Shriram PANDIT , Abhijith PRABHA , Manisha RAIGURU , Ehud RESHEF , Amir RUBIN , Shubham Kumar SAHU , Gurpreet SANDHU , Michael SHACHAR , Harry SKINNER , Madhukiran SRINIVASAREDDY , Gokul SUBRAMANIAM , Maruti TAMRAKAR , Jayprakash THAKUR , Vijaya Prasad UMMELLA , Yagnesh Vinodrai WAGHELA
IPC: H04B1/3827 , H04W52/36
CPC classification number: H04B1/3838 , H04W52/365 , H04B2001/3844
Abstract: Various principles and methods are described herein to improve wireless communication in a user computing device. Certain aspects of the disclosure describe management of wireless transmissions relative to various regulations related to a specific absorption rate. Other aspects of the disclosure relate to detection of user proximity to a transmitting antenna. Other aspects relate to alternative strategies to improve wireless communication, such as selection of alternate antennas or baseband modems, or changes in device orientation.
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Patent Agency Ranking
公开(公告)号：US20250006673A1
公开(公告)日：2025-01-02
申请号：US18343773
申请日：2023-06-29
Applicant: Intel Corporation
IPC: H01L23/00 , H01L21/48 , H01L23/498 , H05K1/02
Abstract: The present disclosure is directed to package-on-package structures having a package substrate with an embedded logic package disposed on the package substrate and having heat conductive pathways being provided in the package-on-package structure for removing heat from the logic package. In an aspect, the heat conductive pathways enable a downward transfer of the heat generated by the logic package toward the package substrate. In another aspect, the heat conducting pathways may include a heat transfer layer formed proximally to a bottom surface of the logic package. In a further aspect, the heat conducting pathways may include one or more metal vias in the package substrate.
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公开(公告)号：US20250006713A1
公开(公告)日：2025-01-02
申请号：US18343770
申请日：2023-06-29
Applicant: Intel Corporation
Abstract: Disclosed herein is a device that provides for high power transfer. The device may include a printed circuit board and a package substrate disposed on the printed circuit board. The device may also include a plurality of high-power voltage regulators disposed on and electrically connected to the package substrate. The device may also include a plurality of low-power voltage regulators disposed on and electrically connected to the printed circuit board.
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公开(公告)号：US20220272880A1
公开(公告)日：2022-08-25
申请号：US17741294
申请日：2022-05-10
Applicant: Intel Corporation
Inventor： Shailendra Singh CHAUHAN , Raghavendra RAO , Ranjul BALAKRISHNAN , Nizamuddin SHAIK , Bijendra SINGH , Siva Prasad JANGILI GANGA , Dong-Ho HAN
IPC: H05K9/00 , H01R12/71 , H01L23/32 , H01L23/498 , H01L23/552 , H05K1/11 , H05K1/14 , H05K1/18
Abstract: A system board includes a module board that connects to the system board with an interposer having compressible connectors. The module board can further be covered by a shield that has a metal alloy having an element to provide good electrical conductivity and an element to provide structural integrity and heat transfer. The module board can further include gaskets to interconnect the shield to a ground plane of the module board. the interposer board can further include an extra column of ground connections to reduce signaling noise between the interposer board and the system board.
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公开(公告)号：US20230006375A1
公开(公告)日：2023-01-05
申请号：US17902503
申请日：2022-09-02
Applicant: Intel Corporation
Inventor： Shailendra Singh CHAUHAN , Bijendra SINGH , Siva Prasad JANGILI GANGA , Santhosh AP , Ranjul BALAKRISHNAN
Abstract: Embodiments of connector-less modules and associated platforms employing the module. The module employs a Land Grid Array (LGA) comprising an array of LGA pins on the underside of the module PCB that are configured to engage respective pads patterned on a motherboard or system board PCB by applying a downward force to the module PCB. A novel clip assembly is provided to apply the downward force, while also aligning the module PCB (and its LGA) to the motherboard or system board PCB. A heat shield is provided that is configured to be disposed over the module PCB to facilitate enhanced thermal spreading and lowering thermal resistance both towards the heat shield and the PCBs. Example modules include a WWAN module and an NVMe SSD module. The module PCB may employ an M.2 form factor or other form factors.
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公开(公告)号：US20220077609A1
公开(公告)日：2022-03-10
申请号：US17479596
申请日：2021-09-20
Applicant: Intel Corporation
Inventor： Navneet Kumar SINGH , Aiswarya M. PIOUS , Richard S. PERRY , Amarjeet KUMAR , Siva Prasad JANGILI GANGA , Gaurav HADA , Sushil PADMANABHAN , Konika GANGULY
Abstract: A connector to connect an electronic module to an edge of a first electronic circuit board is described. The module has a second electronic circuit board. The connector has a top part that houses a first row of I/Os. The top part is to be placed on a surface of the first electronic circuit board. The connector has a bottom part that houses a second row of I/Os. The bottom part is to be placed on an opposite surface of the first electronic circuit board, wherein, the top and bottom parts form inner and outer stand-offs when mater together. The inner stand-off is to reside within a through hole of the first electronic circuit board. The outer stand-off is to reside within free space off the edge of the first electronic circuit board. The second electronic circuit board is to be pressed in between the first row of I/Os and the second row of I/Os when the module is connected to the connector.
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