公开(公告)号：US20250007693A1

公开(公告)日：2025-01-02

申请号：US18217445

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Santosh GHOSH ,  Qian WANG ,  Manoj R. SASTRY

IPC: H04L9/06 ,  H04L9/08 ,  H04L9/30

Abstract: Kyber is a secure key encapsulation mechanism (KEM) for secure key exchange. Performance overhead associated with use of Kyber for secure key exchange is reduced by computing multiple coefficients of different polynomials for independent operations in parallel and localizing them in memory for fast access for polynomial multiplications used in key generation, encapsulation, and decapsulation allowing for parallelization of Keccak calls.

公开(公告)号：US20230400996A1

公开(公告)日：2023-12-14

申请号：US18334262

申请日：2023-06-13

Applicant: Intel Corporation

Inventor： Sergej DEUTSCH ,  David M. DURHAM ,  Karanvir GREWAL ,  Raghunandan MAKARAM ,  Rajat AGARWAL ,  Christoph DOBRAUNIG ,  Krystian MATUSIEWICZ ,  Santosh GHOSH

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0619 ,  G06F3/0679

Abstract: Some aspects of the present disclosure relate to an apparatus comprising interface circuitry and processor circuitry to write data bits to a memory, by applying a diffusion function on the data bits to calculate diffused data bits, calculating error correcting code (ECC) bits based on the data bits or based on the diffused data bits, applying a diffusion function on the ECC bits to calculate diffused ECC bits, storing the diffused ECC bits in an ECC portion of the memory, and storing the data bits or the diffused data bits in a data portion of the memory.

公开(公告)号：US20250141681A1

公开(公告)日：2025-05-01

申请号：US18895438

申请日：2024-09-25

Applicant: Intel Corporation

Inventor： Santosh GHOSH ,  Xiaoyu RUAN ,  Daniel LEIDERMAN ,  Ruben Daniel VARELA VELASCO

IPC: H04L9/14

Abstract: A method and device for generating a shared session secret with forward secrecy between a first device and a second device. The first and second devices perform mutual authentication. The first and second devices establish a first shared secret using a key encapsulation mechanism with a long-term cryptographic key pair of the devices. The first and second devices generate an ephemeral cryptographic key pair comprising an ephemeral public key and an ephemeral private key, respectively, and transfer the ephemeral public key of the device to the other device using the first shared secret. The first and second devices then establish a second shared secret using the key encapsulation mechanism with the ephemeral public keys of the first device and the second device. The second shared secret is used as a temporary shared session secret.

公开(公告)号：US20250112781A1

公开(公告)日：2025-04-03

申请号：US18375317

申请日：2023-09-29

Applicant: INTEL CORPORATION

Inventor： Santosh GHOSH ,  Manoj SASTRY

IPC: H04L9/32

Abstract: A digital signature verification unit or other apparatus of an aspect includes cryptographic hash circuitry to generate cryptographic hashes and multi-scheme hash-based digital signature verification circuitry coupled with the cryptographic hash circuitry. The multi-scheme hash-based digital signature verification circuitry is to use the cryptographic hash circuitry to verify digital signatures according to only one of a plurality of hash-based digital signature verification schemes at a time, the plurality of hash-based digital signature verification schemes including a first hash-based digital signature verification scheme and a second hash-based digital signature verification scheme. Other apparatus, methods, and systems are disclosed.

公开(公告)号：US20250005208A1

公开(公告)日：2025-01-02

申请号：US18217547

申请日：2023-07-01

Applicant: Intel Corporation

Inventor： Dumitru-Daniel DINU ,  Santosh GHOSH ,  Avinash VARNA ,  Manoj SASTRY

IPC: G06F21/75

Abstract: Techniques for improved Keccak execution resilient to physical side-channel attacks are described. In some examples, a Keccak round datapath includes a first path including a theta step, a rho step, a pi step, and an iota step to process a masked version of the 1600-bit input state, a second path including a theta step, a rho step, and a pi step to process a mask 1600-bit input state, and a masked chi step shared by the first path and second path.

公开(公告)号：US20220078201A1

公开(公告)日：2022-03-10

申请号：US17529020

申请日：2021-11-17

Applicant: Intel Corporation

Inventor： Marcio Rogerio Juliato ,  Shabbir AHMED ,  Santosh GHOSH ,  Christopher GUTIERREZ ,  Manoj R. Sastry

IPC: H04L29/06 ,  H04L12/40

Abstract: Various systems and methods for bus-off attack detection are described herein. An electronic device for bus-off attack detection and prevention includes bus-off prevention circuitry coupled to a protected node on a bus, the bus-off prevention circuitry to: detect a transmitted message from the protected node to the bus; detect a bit mismatch of the transmitted message on the bus; suspend further transmissions from the protected node while the bus is analyzed; determine whether the bit mismatch represents a bus fault or an active attack against the protected node; and signal the protected node indicating whether a fault has occurred.