公开(公告)号：US11494212B2

公开(公告)日：2022-11-08

申请号：US16144388

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Ranganath Sunku ,  Dinesh Kumar ,  Irene Liew ,  Kavindya Deegala ,  Sravanthi Tangeda

IPC: G06F9/455 ,  G06F9/50 ,  H04L12/931 ,  G06F15/16 ,  H04L15/16 ,  H04L49/00 ,  H04L41/0823 ,  H04L12/70

Abstract: Technologies for adaptive platform resource management include a compute node to manage a processor core mapping scheme between virtual machines (VMs) and a virtual switch of the compute node via a set of virtual ports. The virtual switch is also coupled to a network interface controller (NIC) of the compute node via another set of virtual ports. Each of the VMs is configured to either provide ingress or egress to the NIC or provide ingress/egress across the VMs, via the virtual ports. The virtual ports for providing ingress or egress to the NIC are pinned to a same processor core of a processor of the compute node, and each of the virtual ports for providing ingress and/or egress across the VMs are pinned to a respective processor core of the processor such that data is transferred across VMs by coupled virtual ports that are pinned to the same processor core.

公开(公告)号：US20190042298A1

公开(公告)日：2019-02-07

申请号：US16144388

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Ranganath Sunku ,  Dinesh Kumar ,  Irene Liew ,  Kavindya Deegala ,  Sravanthi Tangeda

IPC: G06F9/455 ,  G06F9/50 ,  H04L12/931

Abstract: Technologies for adaptive platform resource management include a compute node to manage a processor core mapping scheme between virtual machines (VMs) and a virtual switch of the compute node via a set of virtual ports. The virtual switch is also coupled to a network interface controller (NIC) of the compute node via another set of virtual ports. Each of the VMs is configured to either provide ingress or egress to the NIC or provide ingress/egress across the VMs, via the virtual ports. The virtual ports for providing ingress or egress to the NIC are pinned to a same processor core of a processor of the compute node, and each of the virtual ports for providing ingress and/or egress across the VMs are pinned to a respective processor core of the processor such that data is transferred across VMs by coupled virtual ports that are pinned to the same processor core.