公开(公告)号：US20190050308A1

公开(公告)日：2019-02-14

申请号：US15857885

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Prashant Chaudhari ,  Michael Derr ,  Gustavo Espinosa ,  Balaji Vembu ,  Richard Shannon ,  Bradley Coffman ,  Daniel Knollmueller

IPC: G06F11/263 ,  G06F11/22

CPC classification number: G06F11/263 ,  G06F11/2205 ,  G06F11/2215 ,  G06F11/2284

Abstract: Systems, apparatuses and methods may provide for technology that detects a startup of a system on chip (SoC) and injects, during the startup, one or more domain startup errors into a plurality of domains on the SoC. Additionally, the technology may determine whether the domain startup error(s) were detected during the startup. In one example, the plurality of domains include one or more fabric interfaces.

公开(公告)号：US10678623B2

公开(公告)日：2020-06-09

申请号：US15818429

申请日：2017-11-20

Applicant: Intel Corporation

Inventor： Michael N. Derr ,  Balaji Vembu ,  Michael Mishaeli ,  Brent Chartrand ,  Bryan R White ,  Gustavo Espinosa ,  Prashant D. Chaudhari

IPC: G06F11/07 ,  H04L12/24

Abstract: Various systems and methods for error handling are described herein. A system for error reporting and handling includes a common error handler that handles errors for a plurality of hardware devices, where the common error handler is operable with other parallel error reporting and handling mechanisms. The common error handler may be used to receive an error message from a hardware device, the error message related to an error; identify a source of the error message; identify a class of the error; identify an error definition of the error; determine whether the error requires a diagnostics operation as part of the error handling; initiate the diagnostics operation when the error requires the diagnostics operation; and clear the error at the hardware device.

公开(公告)号：US20190050279A1

公开(公告)日：2019-02-14

申请号：US15818429

申请日：2017-11-20

Applicant: Intel Corporation

Inventor： Michael N. Derr ,  Balaji Vembu ,  Michael Mishaeli ,  Brent Chartrand ,  Bryan R. White ,  Gustavo Espinosa ,  Prashant D. Chaudhari

IPC: G06F11/07

Abstract: Various systems and methods for error handling are described herein. A system for error reporting and handling includes a common error handler that handles errors for a plurality of hardware devices, where the common error handler is operable with other parallel error reporting and handling mechanisms. The common error handler may be used to receive an error message from a hardware device, the error message related to an error; identify a source of the error message; identify a class of the error; identify an error definition of the error; determine whether the error requires a diagnostics operation as part of the error handling; initiate the diagnostics operation when the error requires the diagnostics operation; and clear the error at the hardware device.

公开(公告)号：US10824529B2

公开(公告)日：2020-11-03

申请号：US15857885

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Prashant Chaudhari ,  Michael Derr ,  Gustavo Espinosa ,  Balaji Vembu ,  Richard Shannon ,  Bradley Coffman ,  Daniel Knollmueller

IPC: G06F11/22 ,  G06F11/263

Abstract: Systems, apparatuses and methods may provide for technology that detects a startup of a system on chip (SoC) and injects, during the startup, one or more domain startup errors into a plurality of domains on the SoC. Additionally, the technology may determine whether the domain startup error(s) were detected during the startup. In one example, the plurality of domains include one or more fabric interfaces.