公开(公告)号：US20240202415A1

公开(公告)日：2024-06-20

申请号：US18068601

申请日：2022-12-20

Applicant: Intel Corporation

Inventor： Quan Shi ,  Patrick Morrow ,  Charles Henry Wallace ,  Lars Liebmann ,  Thi Nguyen ,  Sivakumar Venkataraman ,  Nikolay Ryzhenko Vladimirovich ,  Xinning Wang ,  Douglas Stout

IPC: G06F30/392 ,  G06F30/394

CPC classification number: G06F30/392 ,  G06F30/394 ,  G06F2119/18

Abstract: Transistor cell architectures have three MO routing tracks within a single cell height. The cell architectures include at least one p-type transistor formed over a p-type diffusion region and at least one n-type transistor formed over an n-type diffusion region. Each diffusion region extends primarily in a particular direction, and the MO routing tracks extending in the same direction as the diffusion regions. One MO routing track may be formed over each of the diffusion regions, and a third MO routing track formed between the diffusion regions.

公开(公告)号：US20250006721A1

公开(公告)日：2025-01-02

申请号：US18215514

申请日：2023-06-28

Applicant: Intel Corporation

Inventor： Sukru Yemenicioglu ,  Douglas Stout ,  Tai-Hsuan Wu ,  Xinning Wang ,  Ruth Brain ,  Chin-Hsuan Chen ,  Sivakumar Venkataraman ,  Quan Shi ,  Nikolay Ryzhenko Vladimirovich

IPC: H01L27/02 ,  G06F30/392 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

Abstract: Techniques are described for designing and forming cells comprising transistor devices for an integrated circuit. In an example, an integrated circuit structure includes a plurality of cells arranged in rows where some rows have different cell heights compared to other rows. Additionally, the various rows of cells may contain semiconductor nanoribbons having different widths between different rows. For example, any number of first rows of cells can each have a first height and any number of second rows can each have a second height that is smaller than the first height. The first rows of cells may include transistors with semiconductor nanoribbons having a first width and the second rows of cells may include transistors with semiconductor nanoribbons having a second width smaller than the first width. In some cases, any of the first rows of cells may also include transistors with semiconductor nanoribbons having the second width.