公开(公告)号：US20210303053A1

公开(公告)日：2021-09-30

申请号：US16833131

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Christopher Lake ,  Vaibhav Shankar ,  Prashant Kodali

IPC: G06F1/3206 ,  G06F1/3296

Abstract: Techniques and mechanisms for a power management circuit to monitor a power domain during one or more attempts to configure a low power state of the power domain. In an embodiment, the one or more attempts are performed during an instance of a local power state at a processor that is coupled to the power management circuit. The monitoring is to detect for a condition wherein the power domain has been in a power state, other than the low power state, for longer than a predetermined threshold length of time. Where the condition is detected, the power management circuit generates one or more signals which change the local power state of the processor, or interrupt an operating system that is executed with the processor. In another embodiment, the power management circuit provides analytic data based on the monitoring of the one or more attempts.

公开(公告)号：US11086384B2

公开(公告)日：2021-08-10

申请号：US16688452

申请日：2019-11-19

Applicant: Intel Corporation

Inventor： Christopher Lake

IPC: G06F1/3234

Abstract: One embodiment includes hardware logic to: receive first and second communications corresponding to an intellectual property (IP) core and begin a timed session in response to receiving the second communication; determine the firmware has completed processing the second communication before expiration of the timed session and increase a latency state corresponding to a resource in response to determining the firmware has completed processing the second communication before expiration of the timed session; receive a third communication corresponding to the IP core and begin an additional timed session in response to receiving the third communication; determine the firmware failed to complete processing the third communication before expiration of the additional timed session and decrease the latency state corresponding to the resource in response to determining the firmware failed to complete processing the third communication before expiration of the additional timed session.

公开(公告)号：US10545869B2

公开(公告)日：2020-01-28

申请号：US16024672

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Pronay Dutta ,  Christopher Lake ,  Patrick James ,  Paul Crutcher

IPC: G06F12/08 ,  G06F1/3296 ,  G06F9/4401 ,  G06F12/0804

Abstract: A power button override allows a persistent memory enabled platform to preserve data in persistent memory before initiating shutdown in a manner that is transparent to the user. The power button override prevents shutdown until all of the volatile cache and any other data in the platform has been flushed to persistent memory.

公开(公告)号：US11340683B2

公开(公告)日：2022-05-24

申请号：US16833131

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Christopher Lake ,  Vaibhav Shankar ,  Prashant Kodali

IPC: G06F1/3206 ,  G06F1/3296

Abstract: Techniques and mechanisms for a power management circuit to monitor a power domain during one or more attempts to configure a low power state of the power domain. In an embodiment, the one or more attempts are performed during an instance of a local power state at a processor that is coupled to the power management circuit. The monitoring is to detect for a condition wherein the power domain has been in a power state, other than the low power state, for longer than a predetermined threshold length of time. Where the condition is detected, the power management circuit generates one or more signals which change the local power state of the processor, or interrupt an operating system that is executed with the processor. In another embodiment, the power management circuit provides analytic data based on the monitoring of the one or more attempts.

公开(公告)号：US20210149472A1

公开(公告)日：2021-05-20

申请号：US16688452

申请日：2019-11-19

Applicant: Intel Corporation

Inventor： Christopher Lake

IPC: G06F1/3234

Abstract: One embodiment includes hardware logic to: receive first and second communications corresponding to an intellectual property (IP) core and begin a timed session in response to receiving the second communication; determine the firmware has completed processing the second communication before expiration of the timed session and increase a latency state corresponding to a resource in response to determining the firmware has completed processing the second communication before expiration of the timed session; receive a third communication corresponding to the IP core and begin an additional timed session in response to receiving the third communication; determine the firmware failed to complete processing the third communication before expiration of the additional timed session and decrease the latency state corresponding to the resource in response to determining the firmware failed to complete processing the third communication before expiration of the additional timed session.