公开(公告)号：US11562213B2

公开(公告)日：2023-01-24

申请号：US15954767

申请日：2018-04-17

Applicant: INTEL CORPORATION

Inventor： Byoungwon Choe ,  Kwangwoong Park ,  Seokyong Byun

IPC: G06N3/063 ,  G06F12/02 ,  G06N3/04

Abstract: Logic may reduce the size of runtime memory for deep neural network inference computations. Logic may determine, for two or more stages of a neural network, a count of shared block allocations, or shared memory block allocations, that concurrently exist during execution of the two or more stages. Logic may compare counts of the shared block allocations to determine a maximum count of the counts. Logic may reduce inference computation time for deep neural network inference computations. Logic may determine a size for each of the shared block allocations of the count of shared memory block allocations, to accommodate data to store in a shared memory during execution of the two or more stages of the cascaded neural network. Logic may determine a batch size per stage of the two or more stages of a cascaded neural network based on a lack interdependencies between input data.

公开(公告)号：US20190042925A1

公开(公告)日：2019-02-07

申请号：US15954767

申请日：2018-04-17

Applicant: INTEL CORPORATION

Inventor： Byoungwon Choe ,  Kwangwoong Park ,  Seokyong Byun

IPC: G06N3/063 ,  G06N3/04 ,  G06F12/02

Abstract: Logic may reduce the size of runtime memory for deep neural network inference computations. Logic may determine, for two or more stages of a neural network, a count of shared block allocations, or shared memory block allocations, that concurrently exist during execution of the two or more stages. Logic may compare counts of the shared block allocations to determine a maximum count of the counts. Logic may reduce inference computation time for deep neural network inference computations. Logic may determine a size for each of the shared block allocations of the count of shared memory block allocations, to accommodate data to store in a shared memory during execution of the two or more stages of the cascaded neural network. Logic may determine a batch size per stage of the two or more stages of a cascaded neural network based on a lack interdependencies between input data.

公开(公告)号：US20190087729A1

公开(公告)日：2019-03-21

申请号：US15706930

申请日：2017-09-18

Applicant: Intel Corporation

Inventor： Seok-Yong Byun ,  Byungseok Roh ,  Minje Park ,  Byoungwon Choe

IPC: G06N3/08 ,  G05B13/02 ,  G06N3/04

Abstract: Systems and methods are provided that tune a convolutional neural network (CNN) to increase both its accuracy and computational efficiency. In some examples, a computing device storing the CNN includes a CNN tuner that is a hardware and/or software component that is configured to execute a tuning process on the CNN. When executing according to this configuration, the CNN tuner iteratively processes the CNN layer by layer to compress and prune selected layers. In so doing, the CNN tuner identifies and removes links and neurons that are superfluous or detrimental to the accuracy of the CNN.