公开(公告)号：US20180120916A1

公开(公告)日：2018-05-03

申请号：US15373466

申请日：2016-12-09

Applicant: Industrial Technology Research Institute

Inventor： Yung-Chieh Lin ,  Shih-Che Lin ,  Chao-Hong Chen ,  Liang-Chia Cheng

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3287

Abstract: A FPGA-based system power estimation apparatus and a method for estimating the power of a target intellectual property (IP) circuit are provided. The system power estimation apparatus includes a FPGA and a power analysis circuit. The FPGA is configured to accommodate the target IP circuit. The power analysis circuit is disposed into the FPGA. The power analysis circuit retrieves an internal operation-state signal of the target IP circuit. The power analysis circuit examines the internal operation-state signal to determine an operation state of the target IP circuit and uses a power model to convert the operation state of the target IP circuit into at least one power value.

公开(公告)号：US09773080B2

公开(公告)日：2017-09-26

申请号：US14985204

申请日：2015-12-30

Applicant: Industrial Technology Research Institute

Inventor： Yeong-Jar Chang ,  Juin-Ming Lu ,  Liang-Chia Cheng

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5027

Abstract: A thermal simulation device is applied to a transaction-level designed chip which includes a plurality of intellectual properties. The thermal simulation device includes a plurality of thermal-aware transaction-level power model circuits, a simulator, a translator and a thermal emulator. The thermal-aware transaction-level power model circuits corresponds to the respective intellectual properties, and are configured to a corresponding power information for each of the intellectual properties, and dynamically adjusts the power information according to temperature information. The simulator is configured to generate the corresponding temperature information of the intellectual properties according to compatible information. The translator is configured to generate the compatible information which is compatible with the simulator. The thermal emulator is configured to trigger the simulator and transmit the temperature information to the intellectual properties.

公开(公告)号：US10324517B2

公开(公告)日：2019-06-18

申请号：US15373466

申请日：2016-12-09

Applicant: Industrial Technology Research Institute

Inventor： Yung-Chieh Lin ,  Shih-Che Lin ,  Chao-Hong Chen ,  Liang-Chia Cheng

IPC: G06F1/32 ,  G06F1/324 ,  G06F1/3287

Abstract: A FPGA-based system power estimation apparatus and a method for estimating the power of a target intellectual property (IP) circuit are provided. The system power estimation apparatus includes a FPGA and a power analysis circuit. The FPGA is configured to accommodate the target IP circuit. The power analysis circuit is disposed into the FPGA. The power analysis circuit retrieves an internal operation-state signal of the target IP circuit. The power analysis circuit examines the internal operation-state signal to determine an operation state of the target IP circuit and uses a power model to convert the operation state of the target IP circuit into at least one power value.