公开(公告)号：US11675630B2

公开(公告)日：2023-06-13

申请号：US16541979

申请日：2019-08-15

申请人： Intel Corporation

发明人： Michael Behar ,  Moshe Maor ,  Ronen Gabbai ,  Roni Rosner ,  Zigi Walter ,  Oren Agam

IPC分类号： G06F9/50 ,  G06F16/901 ,  G06N3/044 ,  G06N3/045

CPC分类号： G06F9/5083 ,  G06F16/9024 ,  G06N3/044 ,  G06N3/045

摘要： Methods, apparatus, systems and articles of manufacture are disclosed to configure heterogenous components in an accelerator. An example apparatus includes a graph compiler to identify a workload node in a workload and generate a selector for the workload node, and the selector to identify an input condition and an output condition of a compute building block, wherein the graph compiler is to, in response to obtaining the identified input condition and output condition from the selector, map the workload node to the compute building block.

公开(公告)号：US20220237850A1

公开(公告)日：2022-07-28

申请号：US17669126

申请日：2022-02-10

申请人： Intel Corporation

发明人： Uzi Sarel ,  Ehud Cohen ,  Tomer Schwartz ,  Amitai Armon ,  Yahav Shadmiy ,  Itamar Ben-Ari ,  Amit Bleiweiss ,  Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag ,  Michael Behar ,  Guy Jacob ,  Gal Leibovich ,  Jeremie Dreyfuss

IPC分类号： G06T15/00 ,  G06N3/02 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

摘要： In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.

公开(公告)号：US20220076118A1

公开(公告)日：2022-03-10

申请号：US17404153

申请日：2021-08-17

申请人： Intel Corporation

发明人： Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag ,  Jeremie Dreyfuss ,  Amit Bleiweiss ,  Tomer Schwartz ,  Raanan Yonatan Yehezkel Rohekar ,  Michael Behar ,  Amitai Armon ,  Uzi Sarel

IPC分类号： G06N3/08 ,  G06N20/10 ,  G06N20/00

摘要： In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to receive a plurality of data inputs for training a neural network, wherein the data inputs comprise training data and weights inputs; represent the data inputs in a first form; and represent the weight inputs in a second form. Other embodiments are also disclosed and claimed.

公开(公告)号：US11763183B2

公开(公告)日：2023-09-19

申请号：US17390528

申请日：2021-07-30

申请人： Intel Corporation

发明人： Ajit Singh ,  Bharat Daga ,  Michael Behar

IPC分类号： G06N3/08 ,  G06F13/10 ,  G06N3/04 ,  G06N5/046 ,  G06T15/20 ,  G06F17/16 ,  G06F13/28 ,  G06N20/00 ,  G06T9/00

CPC分类号： G06N5/046 ,  G06F13/10 ,  G06F13/28 ,  G06F17/16 ,  G06N3/04 ,  G06N3/08 ,  G06N20/00 ,  G06T9/002 ,  G06T15/205

摘要： Embodiments described herein provide a processing apparatus comprising compute circuitry to generate neural network data for a convolutional neural network (CNN) and write the neural network data to a memory buffer. The compute circuitry additionally includes a direct memory access (DMA) controller including a hardware codec having encode circuitry and a decode circuitry. The DMA controller reads the neural network data from the memory buffer, encode the neural network data via the encode circuit, writes encoded neural network data to a memory device coupled with the processing apparatus, writes metadata for the encoded neural network data to the memory device coupled with the processing apparatus, and decodes encoded neural network data via the decode circuit in response to a request from the compute circuitry.

公开(公告)号：US11600035B2

公开(公告)日：2023-03-07

申请号：US17669126

申请日：2022-02-10

申请人： Intel Corporation

发明人： Uzi Sarel ,  Ehud Cohen ,  Tomer Schwartz ,  Amitai Armon ,  Yahav Shadmiy ,  Itamar Ben-Ari ,  Amit Bleiweiss ,  Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag ,  Michael Behar ,  Guy Jacob ,  Gal Leibovich ,  Jeremie Dreyfuss

IPC分类号： G06N3/04 ,  G06N3/08 ,  G06N3/063 ,  G06T15/00 ,  G06N3/02

摘要： In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.

公开(公告)号：US11238338B2

公开(公告)日：2022-02-01

申请号：US15494887

申请日：2017-04-24

申请人： Intel Corporation

发明人： Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag ,  Jeremie Dreyfuss ,  Amit Bleiweiss ,  Tomer Schwartz ,  Raanan Yonatan Yehezkel Rohekar ,  Michael Behar ,  Amital Armon ,  Uzi Sarel

IPC分类号： G06N3/08 ,  G06N20/00 ,  G06N20/10

摘要： In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to receive a plurality of data inputs for training a neural network, wherein the data inputs comprise training data and weights inputs; represent the data inputs in a first form; and represent the weight inputs in a second form. Other embodiments are also disclosed and claimed.

公开(公告)号：US20210357793A1

公开(公告)日：2021-11-18

申请号：US17390528

申请日：2021-07-30

申请人： Intel Corporation

发明人： Ajit Singh ,  Bharat Daga ,  Michael Behar

IPC分类号： G06N5/04 ,  G06T15/20 ,  G06F17/16 ,  G06F13/28 ,  G06N20/00 ,  G06N3/08 ,  G06F13/10 ,  G06T9/00

摘要： Embodiments described herein provide a processing apparatus comprising compute circuitry to generate neural network data for a convolutional neural network (CNN) and write the neural network data to a memory buffer. The compute circuitry additionally includes a direct memory access (DMA) controller including a hardware codec having encode circuitry and a decode circuitry. The DMA controller reads the neural network data from the memory buffer, encode the neural network data via the encode circuit, writes encoded neural network data to a memory device coupled with the processing apparatus, writes metadata for the encoded neural network data to the memory device coupled with the processing apparatus, and decodes encoded neural network data via the decode circuit in response to a request from the compute circuitry.

公开(公告)号：US11080611B2

公开(公告)日：2021-08-03

申请号：US15853457

申请日：2017-12-22

申请人： Intel Corporation

发明人： Ajit Singh ,  Bharat Daga ,  Michael Behar

IPC分类号： G06N3/08 ,  G06F13/10 ,  G06T9/00 ,  G06N5/04 ,  G06T15/20 ,  G06F17/16 ,  G06F13/28 ,  G06N20/00

摘要： Embodiments described herein provide a processing apparatus comprising compute logic to generate neural network data for a convolutional neural network (CNN) and write the neural network data to a memory buffer. The compute logic additionally includes a direct memory access (DMA) controller including a hardware codec having an encode unit and a decode unit, the DMA controller to read the neural network data from the memory buffer, encode the neural network data via the encode unit, write encoded neural network data to a memory device coupled with the processing apparatus, write metadata for the encoded neural network data to the memory device coupled with the processing apparatus, and decode encoded neural network data via the decode unit in response to a request from the compute logic.

公开(公告)号：US10762685B2

公开(公告)日：2020-09-01

申请号：US16670749

申请日：2019-10-31

申请人： Intel Corporation

发明人： Uzi Sarel ,  Ehud Cohen ,  Tomer Schwartz ,  Amitai Armon ,  Yahav Shadmiy ,  Itamar Ben-Ari ,  Amit Bleiweiss ,  Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag ,  Michael Behar ,  Guy Jacob ,  Gal Leibovich ,  Jeremie Dreyfuss

IPC分类号： G06N3/02 ,  G06N3/08 ,  G06N3/063 ,  G06T15/00 ,  G06N3/04

摘要： In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200143579A1

公开(公告)日：2020-05-07

申请号：US16670749

申请日：2019-10-31

申请人： Intel Corporation

发明人： Uzi Sarel ,  Ehud Cohen ,  Tomer Schwartz ,  Amitai Armon ,  Yahav Shadmiy ,  Itamar Ben-Ari ,  Amit Bleiweiss ,  Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag ,  Michael Behar ,  Guy Jacob ,  Gal Leibovich ,  Jeremie Dreyfuss

IPC分类号： G06T15/00 ,  G06N3/02 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

摘要： In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.