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公开(公告)号:US10148469B2
公开(公告)日:2018-12-04
申请号:US15583644
申请日:2017-05-01
申请人: INTEL CORPORATION
发明人: Mor M. Cohen , Yaniv Hadar , Ehud U. Shoor
摘要: An apparatus is provided which comprises: a data slicer to receive first data sampled by a data clock; an edge slicer to receive second data sampled by an edge clock; and a Least Mean Square (LMS) circuitry coupled to the data and edge slicers, wherein the LSM circuitry is to generate a code to adjust a phase of one of data clock and/or edge clock relative to one another.