公开(公告)号：US09118400B2

公开(公告)日：2015-08-25

申请号：US14490961

申请日：2014-09-19

Applicant: III Holdings 1, LLC

Inventor： Anand P. Narayan ,  Greg Graham ,  David R. Meyer ,  Prashant Jain

IPC: H04B1/7097 ,  G01S5/02 ,  G01S19/22 ,  H04B1/7105 ,  H04B1/7117 ,  H04B1/7093 ,  G01S5/10

CPC classification number: H04B1/7097 ,  G01S5/0215 ,  G01S5/10 ,  G01S19/22 ,  H04B1/7093 ,  H04B1/7105 ,  H04B1/7117 ,  H04B2001/70935 ,  H04B2201/70701 ,  H04B2201/70715

Abstract: An interference cancelling receiver combines data from multiple paths after aligning to transmitter timing, and uses either an equalizer or a Rake receiver to compute symbol estimates. Interference estimates are generated from the symbol estimates, and multiple interference estimates are combined after re-aligning the interference estimates to receiver timing. At least two segments of symbol estimates are computed for each segment of interference cancelled data.Various techniques may be employed for controlling the latency and sequencing of these operations, and the subsystems within the canceller may use different processing clock speeds.

Abstract translation: 干扰消除接收机在对准发射机定时之后组合来自多个路径的数据，并且使用均衡器或Rake接收机来计算符号估计。 从符号估计产生干扰估计，并且在将干扰估计重新对准接收机定时之后组合多个干扰估计。 对干扰消除数据的每个段计算符号估计的至少两个段。 可以采用各种技术来控制这些操作的等待时间和顺序，并且消除器内的子系统可以使用不同的处理时钟速度。