公开(公告)号：US20120119229A1

公开(公告)日：2012-05-17

申请号：US13159317

申请日：2011-06-13

申请人： Hyun-Young Kim ,  Sung-In Ro ,  Cheoll-Hee Jeon

发明人： Hyun-Young Kim ,  Sung-In Ro ,  Cheoll-Hee Jeon

IPC分类号： H01L33/62

CPC分类号： H01L27/1259 ,  G02F1/13458 ,  G02F1/136227 ,  G02F2001/136236 ,  H01L21/28008 ,  H01L21/283 ,  H01L21/4885 ,  H01L27/124 ,  H01L27/1288

摘要： A thin film transistor array panel includes: a substrate including a display area and a drive region in which a driving chip for transmitting a driving signal to the pixels is located; a gate line in the display area; a storage electrode line; a gate driving pad coupled to the driving chip; a gate insulating layer; a first semiconductor layer on the gate insulating layer and overlapped with a gate electrode protruding from the gate line; a second semiconductor layer formed on the gate insulating layer and overlapped with a sustain electrode protruding from the storage electrode line; a data line crossing the gate line in an insulated manner and a drain electrode separated from the data line; and a pixel electrode coupled to the drain electrode, and the drain electrode comprises a drain bar facing the source electrode, and a drain extender overlapped with the second semiconductor layer.

摘要翻译： 薄膜晶体管阵列面板包括：基板，包括显示区域和驱动区域，驱动区域中驱动信号发送到像素的驱动芯片; 显示区域中的栅极线; 存储电极线; 耦合到驱动芯片的栅极驱动焊盘; 栅极绝缘层; 栅极绝缘层上的第一半导体层，并与从栅极线突出的栅电极重叠; 形成在所述栅极绝缘层上并与从所述存储电极线突出的维持电极重叠的第二半导体层; 以绝缘方式与栅极线交叉的数据线和与数据线分离的漏电极; 以及耦合到所述漏电极的像素电极，并且所述漏电极包括面向所述源电极的漏极条和与所述第二半导体层重叠的漏极延伸器。

公开(公告)号：US08581312B2

公开(公告)日：2013-11-12

申请号：US13159317

申请日：2011-06-13

申请人： Hyun-Young Kim ,  Sung-In Ro ,  Cheoll-Hee Jeon

发明人： Hyun-Young Kim ,  Sung-In Ro ,  Cheoll-Hee Jeon

IPC分类号： H01L31/062

CPC分类号： H01L27/1259 ,  G02F1/13458 ,  G02F1/136227 ,  G02F2001/136236 ,  H01L21/28008 ,  H01L21/283 ,  H01L21/4885 ,  H01L27/124 ,  H01L27/1288

摘要： A thin film transistor array panel includes: a substrate including a display area and a drive region in which a driving chip for transmitting a driving signal to the pixels is located; a gate line in the display area; a storage electrode line; a gate driving pad coupled to the driving chip; a gate insulating layer; a first semiconductor layer on the gate insulating layer and overlapped with a gate electrode protruding from the gate line; a second semiconductor layer formed on the gate insulating layer and overlapped with a sustain electrode protruding from the storage electrode line; a data line crossing the gate line in an insulated manner and a drain electrode separated from the data line; and a pixel electrode coupled to the drain electrode, and the drain electrode comprises a drain bar facing the source electrode, and a drain extender overlapped with the second semiconductor layer.