知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

5 条记录 (耗时 0.047 秒)

    Multiple-core, multithreaded processor with flexible error steering mechanism
    1.
    发明授权
    Multiple-core, multithreaded processor with flexible error steering mechanism 有权
    多核多线程处理器，具有灵活的错误转向机制

    公开(公告)号：US07716521B1

    公开(公告)日：2010-05-11

    申请号：US11123674

    申请日：2005-05-06

    申请人： Hunter S. Donahue ,  Ricky C. Hetherington ,  Jimmy K. Lau

    发明人： Hunter S. Donahue ,  Ricky C. Hetherington ,  Jimmy K. Lau

    IPC分类号： G06F11/00

    CPC分类号： G06F11/0793 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3879 ,  G06F9/3885 ,  G06F11/0715 ,  G06F11/0721 ,  G06F11/0724

    摘要： A multiple-core, multithreaded processor including a flexible error steering mechanism. An integrated circuit may include processor cores. Each processor core is associated with a respective number of threads and is configured to issue a first instruction from one of the threads during one execution cycle and a second instruction from another one of the threads during a successive execution cycle. An error processing unit may be coupled to the processor cores and configured to detect an error condition corresponding to a data element external to the processor cores. In response to detecting the error condition, the error processing unit may convey an indication of the error to a selected processor core dependent upon an identifier of the selected core. The error indication may also include an identifier of a selected thread executable on the selected processor core. The identifiers of the selected core and the selected thread may be programmable.

    摘要翻译： 一个多核多线程处理器，包括一个灵活的错误转向机制。 集成电路可以包括处理器核。 每个处理器核心与相应数量的线程相关联，并且被配置为在一个执行周期期间从一个线程发出第一条指令，并且在连续的执行周期期间从另一个线程发出第二条指令。 错误处理单元可以耦合到处理器核并且被配置为检测与处理器核心外部的数据元素相对应的错误状况。 响应于检测到错误状况，错误处理单元可以根据所选择的核心的标识符将错误的指示传送到所选择的处理器核心。 错误指示还可以包括在所选择的处理器核心上可执行的所选线程的标识符。 所选择的核心和所选线程的标识符可以是可编程的。

    Entertainment Control System and Related Methods
    2.
    发明申请
    Entertainment Control System and Related Methods 审中-公开
    娱乐控制系统及相关方法

    公开(公告)号：US20110072482A1

    公开(公告)日：2011-03-24

    申请号：US12861831

    申请日：2010-08-24

    申请人： Jimmy K. Lau

    发明人： Jimmy K. Lau

    IPC分类号： H04N7/173

    CPC分类号： H04N21/4222 ,  H04N21/43615 ,  H04N21/43635 ,  H04N21/43637

    摘要： In some examples, a control system comprises a first unit and a second unit. The first unit comprises a command input configured to receive one or more commands from one or more command devices of a command device array, and a first transceiver configured to transmit one or more encoded commands. The second unit second unit comprises a second transceiver configured to receive the one or more encoded commands from the first transceiver, and a command output configured to output one or more decoded commands to a content source array. The first and second units are separate from each other. The one or more encoded commands correspond to the one or more commands, the one or more decoded commands correspond to the one or more encoded commands, and the content source array comprises one or more content sources. Other examples and related methods are described herein.

    摘要翻译： 在一些示例中，控制系统包括第一单元和第二单元。 第一单元包括被配置为从命令装置阵列的一个或多个命令装置接收一个或多个命令的命令输入和被配置为发送一个或多个编码命令的第一收发器。 第二单元第二单元包括被配置为从第一收发器接收一个或多个编码命令的第二收发器和被配置为将一个或多个解码的命令输出到内容源阵列的命令输出。 第一和第二单元彼此分开。 一个或多个编码命令对应于一个或多个命令，一个或多个解码的命令对应于一个或多个编码命令，并且内容源阵列包括一个或多个内容源。 本文描述了其它实例和相关方法。