公开(公告)号：US20220262751A1

公开(公告)日：2022-08-18

申请号：US17733132

申请日：2022-04-29

Applicant: Huawei Technologies Co., Ltd.

Inventor： Tonglong Zhang ,  Xiaodong Zhang ,  Yong Guan ,  Simin Wang

IPC: H01L23/00 ,  H01L25/10

Abstract: A chip package on package structure includes a primary chip stack unit having pins insulated and spaced from each other on a first surface; a first bonding layer disposed on the first surface, where the first bonding layer includes bonding components insulated and spaced from each other, each bonding component includes a bonding part, and any two bonding parts are insulated and have a same cross-sectional area, and the bonding components are separately bonded to the pins; and secondary chip stack units, disposed on a surface of a side that is of the first bonding layer and that is away from the primary chip stack unit, where the secondary chip stack unit has micro bumps insulated and spaced from each other, and each of the micro bumps is bonded to one of the bonding components.

公开(公告)号：US20220189901A1

公开(公告)日：2022-06-16

申请号：US17687220

申请日：2022-03-04

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shiqun Gu ,  Rui Niu ,  Xiaodong Zhang ,  Yiwei Ren ,  Tonglong Zhang

IPC: H01L23/00 ,  H01L23/538 ,  H01L25/10 ,  H01L25/065 ,  H01L25/00

Abstract: A packaged IC includes a fanout layer, a processor having a first surface residing substantially adjacent a first surface of the fanout layer, a Redistribution Layer (RDL) having a first surface coupled to a second surface of the processor, and a memory coupled to a second surface of the RDL, wherein a first portion of the memory is disposed outside of a footprint of the processor and a second portion of the memory is disposed within the footprint of the processor. The packaged IC further includes first conductive posts disposed beneath the first portion of the memory proximate a first side of the processor for providing communication links between the processor and memory, and second conductive posts coupled between the fanout layer and conductive features of the RDL coupled to power inputs of the second portion of the memory, the second conductive posts proximate a second side of the processor.

公开(公告)号：US20220077123A1

公开(公告)日：2022-03-10

申请号：US17531133

申请日：2021-11-19

Applicant: Huawei Technologies Co., Ltd.

Inventor： Tonglong Zhang ,  Xiaodong Zhang ,  Yong Guan ,  Heng Li

IPC: H01L25/10 ,  H01L23/29 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00

Abstract: A chip package structure includes a first chip, a second chip, and a carrier board. The first chip is disposed between the second chip and the carrier board. An active layer of the first chip is opposite to an active layer of the second chip. A first interconnection structure is disposed between the first chip and the second chip and is configured to couple the active layer of the first chip to the active layer of the second chip. A first conductor pillar is disposed in the first chip. One end of the first conductor pillar is coupled to the active layer of the first chip, and the other end of the first conductor passes through the first chip to be coupled to a circuit in the carrier board.