公开(公告)号：US10426036B2

公开(公告)日：2019-09-24

申请号：US16192018

申请日：2018-11-15

Applicant: Huawei Technologies Co., Ltd.

Inventor： Songlin Li ,  Pengbo Tian ,  Qingyun Wang ,  Liang Xu

IPC: H03F3/22 ,  H05K1/18 ,  H05K3/34

Abstract: A power tube connection structure includes a substrate, a printed circuit board, and a power tube, where a through groove allowing the power tube to pass through is cut into the printed circuit board, a mounting groove is cut into the upper surface of the substrate at a location corresponding to the through groove, one end of the power tube extends through the through groove, and is welded onto a bottom face of the mounting groove, the end of the power tube that extends into the mounting groove abuts onto a side wall of the mounting groove close to an output end of the power amplifier, and a solder flux escape channel is made into the side wall of the mounting groove close to the output end of the power amplifier.

公开(公告)号：US10165687B2

公开(公告)日：2018-12-25

申请号：US15676352

申请日：2017-08-14

Applicant: Huawei Technologies Co., Ltd.

Inventor： Songlin Li ,  Pengbo Tian ,  Qingyun Wang ,  Liang Xu

IPC: H05K1/18 ,  H03F3/22 ,  H05K3/34

Abstract: A power tube connection structure includes a substrate, a printed circuit board, and a power tube, where a through groove allowing the power tube to pass through is cut into the printed circuit board, a mounting groove is cut into the upper surface of the substrate at a location corresponding to the through groove, one end of the power tube extends through the through groove, and is welded onto a bottom face of the mounting groove, the end of the power tube that extends into the mounting groove abuts onto a side wall of the mounting groove close to an output end of the power amplifier, and a solder flux escape channel is made into the side wall of the mounting groove close to the output end of the power amplifier.

公开(公告)号：US08916970B2

公开(公告)日：2014-12-23

申请号：US14104237

申请日：2013-12-12

Applicant: Huawei Technologies Co., Ltd.

Inventor： Lungang Yun ,  An Huang ,  Pengbo Tian

IPC: H01L23/48 ,  H01L21/00 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L24/83 ,  H01L2924/01322 ,  H01L2924/1306 ,  H01L2924/00

Abstract: Relating to electronic components, the present disclosure provides a method for welding a gold-silicon eutectic chip, and a transistor. The method for welding a gold-silicon eutectic chip includes: electroplating a gold layer with a thickness smaller than or equal to 1 micron on surfaces of a chip carrier; bonding multiple gold protrusions on the gold layer in a welding region; and rubbing a chip in the welding region at a eutectic temperature to form a welding layer. The transistor includes a chip, a chip carrier, and a middle layer connecting the chip and the chip carrier, where the welding middle layer is a welding layer obtained by using the above welding method. The present disclosure reduces an amount of gold in use and lowers a cost of gold-silicon eutectic welding to a relatively large extent, and, accordingly, cuts down the cost of a transistor.

Abstract translation: 关于电子元件，本公开提供了一种用于焊接金 - 硅共晶芯片和晶体管的方法。 用于焊接金 - 硅共晶芯片的方法包括：在芯片载体的表面上电镀厚度小于或等于1微米的金层; 在焊接区域的金层上粘合多个金突起; 并在共晶温度下在焊接区域中摩擦芯片以形成焊接层。 晶体管包括芯片，芯片载体和连接芯片和芯片载体的中间层，其中焊接中间层是通过使用上述焊接方法获得的焊接层。 本公开减少了使用中的金的量，并且相对较大程度地降低了金 - 硅共晶焊接的成本，并因此降低了晶体管的成本。

公开(公告)号：US20140175641A1

公开(公告)日：2014-06-26

申请号：US14104237

申请日：2013-12-12

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Lungang Yun ,  An Huang ,  Pengbo Tian

IPC: H01L23/498 ,  H01L21/02

CPC classification number: H01L23/49811 ,  H01L24/83 ,  H01L2924/01322 ,  H01L2924/1306 ,  H01L2924/00

Abstract: Relating to electronic components, the present disclosure provides a method for welding a gold-silicon eutectic chip, and a transistor. The method for welding a gold-silicon eutectic chip includes: electroplating a gold layer with a thickness smaller than or equal to 1 micron on surfaces of a chip carrier; bonding multiple gold protrusions on the gold layer in a welding region; and rubbing a chip in the welding region at a eutectic temperature to form a welding layer. The transistor includes a chip, a chip carrier, and a middle layer connecting the chip and the chip carrier, where the welding middle layer is a welding layer obtained by using the above welding method. The present disclosure reduces an amount of gold in use and lowers a cost of gold-silicon eutectic welding to a relatively large extent, and, accordingly, cuts down the cost of a transistor.

Abstract translation: 关于电子元件，本公开提供了一种用于焊接金 - 硅共晶芯片和晶体管的方法。 用于焊接金 - 硅共晶芯片的方法包括：在芯片载体的表面上电镀厚度小于或等于1微米的金层; 在焊接区域的金层上粘合多个金突起; 并在共晶温度下在焊接区域中摩擦芯片以形成焊接层。 晶体管包括芯片，芯片载体和连接芯片和芯片载体的中间层，其中焊接中间层是通过使用上述焊接方法获得的焊接层。 本公开减少了使用中的金的量，并且相对较大程度地降低了金 - 硅共晶焊接的成本，并因此降低了晶体管的成本。