公开(公告)号：US20230012986A1

公开(公告)日：2023-01-19

申请号：US17950610

申请日：2022-09-22

Applicant: Huawei Technologies Co., Ltd.

Inventor： Heng LI ,  Xiaodong ZHANG ,  Tonglong ZHANG ,  Simin WANG

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L21/56

Abstract: This disclosure provides a chip structure, including a first chip and a first protective layer, where the first protective layer covers a first surface of the first chip; and a first conductive connector is vertically disposed in the first protective layer, the first conductive connector penetrates through an upper surface and a lower surface of the first protective layer, one end of the first conductive connector is electrically connected to the first surface of the first chip, the other end of the first conductive connector is exposed to the first protective layer, and the first protective layer is formed by a material whose modulus is greater than a preset value.

公开(公告)号：US20190273044A1

公开(公告)日：2019-09-05

申请号：US16415587

申请日：2019-05-17

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： HuiLi FU ,  Heng LI ,  Xiaodong ZHANG

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00

Abstract: Example chip package structure and packaging methods are described. One example chip package structure includes: a redistribution layer (RDL) and a target chip including an active surface and a back surface, where the active surface of the target chip is connected to a first surface of the RDL. The example chip package structure further includes a substrate, where a first surface of the substrate is opposite to the back surface of the target chip. The example chip package structure further includes an interconnection channel that is located around the target chip. One end of the interconnection channel is connected to the first surface of the RDL, and the other end of the interconnection channel is connected to the first surface of the substrate.