Series circuit and computing device

    公开(公告)号:US11243588B2

    公开(公告)日:2022-02-08

    申请号:US15993124

    申请日:2018-05-30

    Abstract: A series circuit and a computing device includes a power supply terminal, a ground terminal and a first connection line for separately connecting a first predetermined number of chips of the plurality of chips in series. A communication line is connected between adjacent chips of the first predetermined number of chips. A portion of the communication line is connected to a target connection point, which is disposed on the first connection line and adapted to the adjacent chips, via a second connection line, and the voltage at the target connection point is greater than or equal to the minimum voltage required for communication between the adjacent chips.

    Series circuit and computing device

    公开(公告)号:US11698670B2

    公开(公告)日:2023-07-11

    申请号:US17563898

    申请日:2021-12-28

    CPC classification number: G06F1/26 H03K19/0185

    Abstract: The present invention discloses a series circuit and a computing device, including: a power supply terminal for providing voltage for a plurality of chips disposed on the computing device; a ground terminal disposed at one end of each of the plurality of chips relative to the power supply terminal; and a first connection line for separately connecting a first predetermined number of chips of the plurality of chips in series, wherein a communication line is connected between adjacent chips of the first predetermined number of chips, a portion of the communication line is connected to a target connection point, which is disposed on the first connection line and adapted to the adjacent chips, via a third connection line, and the voltage at the target connection point is greater than or equal to the minimum voltage required for communication between the adjacent chips. Such circuit structure can be used to provide the voltage required for communication between adjacent chips, while ensuring the same voltage between chips. Therefore, there is no need to provide an auxiliary power supply for each chip or to use a number of signal level conversion devices, thereby reducing the costs.

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