公开(公告)号：US08823437B2

公开(公告)日：2014-09-02

申请号：US13754524

申请日：2013-01-30

Applicant: Huawei Technologies Co., Ltd.

Inventor： Wei Cao ,  Jindi Zhang ,  Yingyan Shan

IPC: G06F1/04 ,  H03L7/099 ,  H03B21/02 ,  H03L7/18 ,  G06F1/06

CPC classification number: H03B21/02 ,  G06F1/06 ,  G06F1/08 ,  H03K21/023 ,  H03K21/12 ,  H03K21/38 ,  H03K23/54 ,  H03L7/0995 ,  H03L7/0998 ,  H03L7/18

Abstract: Embodiments of the present invention provide a clock signal generator, and the clock signal generator is applied to a physical layer subsystem supporting data transmission at multiple baud rates. The clock signal generator includes: a source clock signal generator, and two or more processors connected to an output end of the source clock signal generator; where the source clock signal generator outputs multiple source clock signals with the same frequency according to a reference signal of a reference clock in the subsystem; the processors perform frequency dividing processing on the multiple source clock signals through a digital logic circuit according to an oversampling technology, to obtain a synchronous clock signal corresponding to a baud rate of data transmission in the subsystem, so as to implement timing and transceiving functions when data is transmitted at the baud rate.

Abstract translation: 本发明的实施例提供一种时钟信号发生器，并且时钟信号发生器被应用于以多个波特率支持数据传输的物理层子系统。 时钟信号发生器包括：源时钟信号发生器和连接到源时钟信号发生器输出端的两个或多个处理器; 其中源时钟信号发生器根据子系统中的参考时钟的参考信号输出具有相同频率的多个源时钟信号; 处理器通过数字逻辑电路根据过采样技术对多源时钟信号进行分频处理，以获得与子系统中数据传输的波特率相对应的同步时钟信号，以便实现定时和收发功能， 数据以波特率传输。

公开(公告)号：US20130278302A1

公开(公告)日：2013-10-24

申请号：US13754524

申请日：2013-01-30

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Wei Cao ,  Jindi Zhang ,  Yingyan Shan

IPC: H03B21/02

CPC classification number: H03B21/02 ,  G06F1/06 ,  G06F1/08 ,  H03K21/023 ,  H03K21/12 ,  H03K21/38 ,  H03K23/54 ,  H03L7/0995 ,  H03L7/0998 ,  H03L7/18

Abstract: Embodiments of the present invention provide a clock signal generator, and the clock signal generator is applied to a physical layer subsystem supporting data transmission at multiple baud rates. The clock signal generator includes: a source clock signal generator, and two or more processors connected to an output end of the source clock signal generator; where the source clock signal generator outputs multiple source clock signals with the same frequency according to a reference signal of a reference clock in the subsystem; the processors perform frequency dividing processing on the multiple source clock signals through a digital logic circuit according to an oversampling technology, to obtain a synchronous clock signal corresponding to a baud rate of data transmission in the subsystem, so as to implement timing and transceiving functions when data is transmitted at the baud rate.

Abstract translation: 本发明的实施例提供一种时钟信号发生器，并且时钟信号发生器被应用于以多个波特率支持数据传输的物理层子系统。 时钟信号发生器包括：源时钟信号发生器和连接到源时钟信号发生器输出端的两个或多个处理器; 其中源时钟信号发生器根据子系统中的参考时钟的参考信号输出具有相同频率的多个源时钟信号; 处理器通过数字逻辑电路根据过采样技术对多源时钟信号进行分频处理，以获得与子系统中数据传输的波特率相对应的同步时钟信号，以便实现定时和收发功能， 数据以波特率传输。