DATA COMPRESSION METHOD, DATA DECOMPRESSION METHOD, AND RELATED APPARATUS, ELECTRONIC DEVICE, AND SYSTEM

    公开(公告)号:US20210152183A1

    公开(公告)日:2021-05-20

    申请号:US17162153

    申请日:2021-01-29

    Abstract: A data compression method is disclosed, in the data compression method, a raw data block in raw data is processed based on a compression algorithm to obtain a standard compressed data block that has a length of L2 and that corresponds to the raw data block, and the raw data is further compressed into one or more standard compressed data blocks that each have the length of L2 and that are to be decompressed in parallel by a decompression apparatus, where the decompression apparatus includes a plurality of decompression engines, and each decompression engine is capable of decompressing one standard compressed data block within one processing cycle. According to the data compression method in the embodiments of the present disclosure, a standard compressed data block with a fixed length can be obtained through compression.

    METHOD, CIRCUIT, AND SOC FOR PERFORMING MATRIX MULTIPLICATION OPERATION

    公开(公告)号:US20220391471A1

    公开(公告)日:2022-12-08

    申请号:US17841162

    申请日:2022-06-15

    Abstract: A method for performing a matrix multiplication operation is provided. The method includes: obtaining a matrix B1, a matrix A2, and an index matrix, wherein the index matrix comprises indexes, in a matrix A1, of elements in the matrix A2; generating m matrices B2 based on the index matrix and the matrix B1, wherein the m matrices B2 are all matrices with t rows and n columns, and each row of each matrix B2 is a row indicated in the matrix B1 by a corresponding element in the index matrix; and generating a matrix C based on the matrix A2 and the m matrices B2, wherein the matrix C is a product of the matrix A1 and the matrix B1.

    METHOD, CIRCUIT, AND SOC FOR PERFORMING MATRIX MULTIPLICATION OPERATION

    公开(公告)号:US20220129523A1

    公开(公告)日:2022-04-28

    申请号:US17568538

    申请日:2022-01-04

    Abstract: A method for performing a matrix multiplication operation is provided. The method includes: obtaining a matrix B1, a matrix A2, and an index matrix, wherein the index matrix comprises indexes, in a matrix A1, of elements in the matrix A2; generating m matrices B2 based on the index matrix and the matrix B1, wherein the m matrices B2 are all matrices with t rows and n columns, and each row of each matrix B2 is a row indicated in the matrix B1 by a corresponding element in the index matrix; and generating a matrix C based on the matrix A2 and the m matrices B2, wherein the matrix C is a product of the matrix A1 and the matrix B1.

    METHOD, CIRCUIT, AND SOC FOR PERFORMING MATRIX MULTIPLICATION OPERATION

    公开(公告)号:US20210271736A1

    公开(公告)日:2021-09-02

    申请号:US17324533

    申请日:2021-05-19

    Abstract: A method for performing a matrix multiplication operation is provided. The method includes: obtaining a matrix B1, a matrix A2, and an index matrix, wherein the index matrix comprises indexes, in a matrix A1, of elements in the matrix A2; generating m matrices B2 based on the index matrix and the matrix B1, wherein the m matrices B2 are all matrices with t rows and n columns, and each row of each matrix B2 is a row indicated in the matrix B1 by a corresponding element in the index matrix; and generating a matrix C based on the matrix A2 and the m matrices B2, wherein the matrix C is a product of the matrix A1 and the matrix B1.

    Convolution Operation Chip And Communications Device

    公开(公告)号:US20190317732A1

    公开(公告)日:2019-10-17

    申请号:US16456119

    申请日:2019-06-28

    Abstract: A convolution operation chip (300) and a communications device are provided. The convolution operation chip (300) includes: an M×N multiplication accumulator array (320), including a first multiplication accumulation window, where a processing element PEX,Y of the first multiplication accumulation window is configured to: perform a multiplication operation on convolutional data of the PEX,Y and a convolutional parameter of the PEX,Y, transmit the convolutional parameter of the PEX,Y to a PEX,Y+1, transmit the convolutional data of the PEX,Y to a PEX−1,Y+1, and respectively use the convolutional parameter of the PEX,Y and the convolutional data of the PEX,Y as multipliers of multiplication operations performed by the PEX,Y+1 and the PEX−1,Y+1; a data cache module (310), configured to transmit convolutional data and a convolutional parameter to the first multiplication accumulation window; and an output control module (330), configured to output a convolutional result.

Patent Agency Ranking