摘要:
A method reduces consumption of computational resources in a satellite signal receiver. The method includes segmenting a sample of a received global positioning base band vector, segmenting a sample of a replica code/acquisition signal into segments corresponding in length to the segments of the base band vector, circularly correlating segments of the base band vector to zero padded segments of the code/acquisition signal to form a time domain correlation vector, inserting a portion of the time domain correlation vector in a matrix, continuing to correlate circularly the segments of the received signal sample with zero padded segments of the code signal sample until all of the segments in received signal sample have been circularly correlated, dividing rows in the matrix into blocks that are equal to a smallest increment corresponding to a bit edge, sorting the blocks from the divided rows into zero padded blocks, transforming the zero padded blocks into frequency domain columns, summing the frequency domain columns in different combinations to form a plurality of coherent integration matrices for testing possible bit edge locations and bit values.
摘要:
A method reduces consumption of computational resources in a satellite signal receiver. The method includes segmenting a sample of a received global positioning base band vector, segmenting a sample of a replica code/acquisition signal into segments corresponding in length to the segments of the base band vector, circularly correlating segments of the base band vector to zero padded segments of the code/acquisition signal to form a time domain correlation vector, inserting a portion of the time domain correlation vector in a matrix, continuing to correlate circularly the segments of the received signal sample with zero padded segments of the code signal sample until all of the segments in received signal sample have been circularly correlated, dividing rows in the matrix into blocks that are equal to a smallest increment corresponding to a bit edge, sorting the blocks from the divided rows into zero padded blocks, transforming the zero padded blocks into frequency domain columns, summing the frequency domain columns in different combinations to form a plurality of coherent integration matrices for testing possible bit edge locations and bit values.