公开(公告)号：US20220292226A1

公开(公告)日：2022-09-15

申请号：US17633541

申请日：2020-10-31

Applicant: Google LLC

Inventor： Scott D. Johnson ,  Timothy Jay Chen ,  Mark David Hayter ,  Dominic Anthony Rizzo ,  Eunchan Kim ,  Michael Stefano Fritz Schaffner

IPC: G06F21/76 ,  G06F21/85 ,  G06F21/60

Abstract: An IC chip can provide silicon root of trust (RoT) functionality. In described implementations, the IC chip includes a processor, an interconnect, and multiple peripheral devices. These comportable circuit components are designed to facilitate interoperability and consistent, expected communications for security circuitry. Each peripheral device includes an interface that adheres to a common framework for interacting with the processor and with other peripheral devices. The interface includes an interconnect interface coupling the peripheral device to the interconnect and an inter-device interface coupling the peripheral device to at least one other peripheral device. The peripheral device is realized based on a peripheral device design code that indicates inter-device signaling in accordance with an inter-device scheme of an interface specification. Manufacturers fabricate the peripheral device, based on the design code, to be physically and logically coupled to another peripheral device in a predictable manner This fosters more-robust and reliable security circuitry.

公开(公告)号：US20210397718A1

公开(公告)日：2021-12-23

申请号：US17462698

申请日：2021-08-31

Applicant: Google LLC

Inventor： Marius P. Schilder ,  Timothy Chen ,  Scott D. Johnson ,  Derek L. Martin

IPC: G06F21/57 ,  H04L9/06 ,  G06F21/56 ,  G06F21/51

Abstract: Systems, apparatuses, and methods for improving security of a silicon-based system by creating a glitch-resistant process for executing a software code block on the silicon-based system are disclosed. An example method may begin by marking the software code block as non-executable. Second, intent to execute the software code block is registered with a staging register. Third, the software code block is compressed into a compression constant. Fourth, the compression constant is compared with a first predetermined value using two comparators. Fifth, responsive to the comparators providing a true result after comparison, the software code block is marked as executable to allow the software code block to execute. In another aspect, the example method may be repeated for n>1 iterations, and in each iteration i, an ith software code block is compressed into an ith compression constant that is compared to an ith predetermined value.

公开(公告)号：US11157627B2

公开(公告)日：2021-10-26

申请号：US15898858

申请日：2018-02-19

Applicant: Google LLC

Inventor： Marius P. Schilder ,  Timothy Chen ,  Scott D. Johnson ,  Derek L. Martin

IPC: H04L9/06 ,  G06F21/51 ,  G06F21/57 ,  G06F21/56

Abstract: Systems, apparatuses, and methods for improving security of a silicon-based system by creating a glitch-resistant process for executing a software code block on the silicon-based system are disclosed. An example method may begin by marking the software code block as non-executable. Second, intent to execute the software code block is registered with a staging register. Third, the software code block is compressed into a compression constant. Fourth, the compression constant is compared with a first predetermined value using two comparators. Fifth, responsive to the comparators providing a true result after comparison, the software code block is marked as executable to allow the software code block to execute. In another aspect, the example method may be repeated for n>1 iterations, and in each iteration i, an ith software code block is compressed into an ith compression constant that is compared to an ith predetermined value.

公开(公告)号：US12153720B2

公开(公告)日：2024-11-26

申请号：US17633541

申请日：2020-10-31

Applicant: Google LLC

Inventor： Scott D. Johnson ,  Timothy Jay Chen ,  Mark David Hayter ,  Dominic Anthony Rizzo ,  Eunchan Kim ,  Michael Stefano Fritz Schaffner

IPC: G06F21/76 ,  G06F21/60 ,  G06F21/85

Abstract: An IC chip can provide silicon root of trust (RoT) functionality. In described implementations, the IC chip includes a processor, an interconnect, and multiple peripheral devices. These comportable circuit components are designed to facilitate interoperability and consistent, expected communications for security circuitry. Each peripheral device includes an interface that adheres to a common framework for interacting with the processor and with other peripheral devices. The interface includes an interconnect interface coupling the peripheral device to the interconnect and an inter-device interface coupling the peripheral device to at least one other peripheral device. The peripheral device is realized based on a peripheral device design code that indicates inter-device signaling in accordance with an inter-device scheme of an interface specification. Manufacturers fabricate the peripheral device, based on the design code, to be physically and logically coupled to another peripheral device in a predictable manner. This fosters more-robust and reliable security circuitry.

公开(公告)号：US10854251B2

公开(公告)日：2020-12-01

申请号：US15844118

申请日：2017-12-15

Applicant: Google LLC

Inventor： Andy Yang ,  Scott D. Johnson ,  Lynn Bos ,  Neal Mueller

IPC: G06F17/50 ,  G11C8/20 ,  H04L29/06 ,  G06F21/44 ,  G06K9/00 ,  G11C7/24 ,  G06F21/71

Abstract: This document describes techniques for authenticating an identity of a semiconductor component using a physical identifier. In some aspects, a physical identifier comprised of a region of features located indiscriminately within a surface of an encapsulated semiconductor component is fabricated. The physical identifier is then mapped. The map is then stored for use when authenticating the identity of the semiconductor component.

公开(公告)号：US20190306161A1

公开(公告)日：2019-10-03

申请号：US16412686

申请日：2019-05-15

Applicant: Google LLC

Inventor： Erica Wickstrom Brand ,  Marius Paul Michiel Schilder ,  Scott D. Johnson ,  Vincent Palatin

IPC: H04L29/06 ,  H04W12/04 ,  H04W12/06 ,  H04W4/80

Abstract: Techniques and apparatuses are described that enable integrated second factor authentication. These techniques and apparatuses enable the improved security of something you have without the accompanying inconvenience or chance of loss. To do so, a secure physical entity is integrated within a computing device. While this provides the something you have without a need to carry a separate object with you, the something you have also must not be able to be accessed remotely. To prevent remote access physical wires are connected from the secure physical entity to physical structures on the computing device. In this way, a hacker or cyber thief cannot convince an authentication system that the cyber attacker does indeed have the something you have because to do so the attacker must be in physical possession of the computing device.

公开(公告)号：US20180253557A1

公开(公告)日：2018-09-06

申请号：US15898858

申请日：2018-02-19

Applicant: Google LLC

Inventor： Marius P. Schilder ,  Timothy Chen ,  Scott D. Johnson ,  Derek L. Martin

IPC: G06F21/57 ,  G06F21/56 ,  H04L9/06

CPC classification number: G06F21/577 ,  G06F21/51 ,  G06F21/563 ,  G06F21/567 ,  G06F21/575 ,  H04L9/0643

Abstract: Systems, apparatuses, and methods for improving security of a silicon-based system by creating a glitch-resistant process for executing a software code block on the silicon-based system are disclosed. An example method may begin by marking the software code block as non-executable. Second, intent to execute the software code block is registered with a staging register. Third, the software code block is compressed into a compression constant. Fourth, the compression constant is compared with a first predetermined value using two comparators. Fifth, responsive to the comparators providing a true result after comparison, the software code block is marked as executable to allow the software code block to execute. In another aspect, the example method may be repeated for n>1 iterations, and in each iteration i, an ith software code block is compressed into an ith compression constant that is compared to an ith predetermined value.

公开(公告)号：US20250097218A1

公开(公告)日：2025-03-20

申请号：US18962359

申请日：2024-11-27

Applicant: Google LLC

Inventor： Erica Wickstrom Brand ,  Marius Paul Michiel Schilder ,  Scott D. Johnson ,  Vincent Palatin

IPC: H04L9/40 ,  G06F21/34 ,  H04W4/80 ,  H04W12/041 ,  H04W12/069 ,  H04W12/68

Abstract: Techniques and apparatuses are described that enable integrated second factor authentication. These techniques and apparatuses enable the improved security of something you have without the accompanying inconvenience or chance of loss. To do so, a secure physical entity is integrated within a computing device. While this provides the something you have without a need to carry a separate object with you, the something you have also must not be able to be accessed remotely. To prevent remote access physical wires are connected from the secure physical entity to physical structures on the computing device. In this way, a hacker or cyber thief cannot convince an authentication system that the cyber attacker does indeed have the something you have because to do so the attacker must be in physical possession of the computing device.

公开(公告)号：US12032704B2

公开(公告)日：2024-07-09

申请号：US17462698

申请日：2021-08-31

Applicant: Google LLC

Inventor： Marius P. Schilder ,  Timothy Chen ,  Scott D. Johnson ,  Derek L Martin

IPC: G06F21/51 ,  G06F21/56 ,  G06F21/57 ,  H04L9/06

CPC classification number: G06F21/577 ,  G06F21/51 ,  G06F21/563 ,  G06F21/567 ,  G06F21/575 ,  H04L9/0643

Abstract: Systems, apparatuses, and methods for improving security of a silicon-based system by creating a glitch-resistant process for executing a software code block on the silicon-based system are disclosed. An example method may begin by marking the software code block as non-executable. Second, intent to execute the software code block is registered with a staging register. Third, the software code block is compressed into a compression constant. Fourth, the compression constant is compared with a first predetermined value using two comparators. Fifth, responsive to the comparators providing a true result after comparison, the software code block is marked as executable to allow the software code block to execute. In another aspect, the example method may be repeated for n>1 iterations, and in each iteration i, an ith software code block is compressed into an ith compression constant that is compared to an ith predetermined value.

公开(公告)号：US11972033B2

公开(公告)日：2024-04-30

申请号：US17633530

申请日：2020-10-31

Applicant: Google LLC

Inventor： Scott D. Johnson ,  Timothy Jay Chen ,  Christopher Gori ,  Eunchan Kim ,  Michael Stefano Fritz Schaffner

IPC: G06F21/76 ,  G06F21/60 ,  G06F21/85

CPC classification number: G06F21/76 ,  G06F21/602 ,  G06F21/85

Abstract: An IC chip can provide silicon root of trust (RoT) functionality. In described implementations, the IC chip includes a processor, an alert handler, and multiple peripheral devices, which generate alert indications. The alert handler processes the alert indications, which have security implications. The alert handler includes multiple alert receiver modules to communicate with the multiple peripheral devices. The alert handler also includes a controller, multiple accumulation units, multiple escalation timers, and multiple escalation sender modules. These components can be organized into a hierarchy of increasing escalation severity. In operation, the controller classifies an alert and flexibly implements an adaptable alert handler path that is established through the escalation components responsive to the classification and based on a source of the alert. A path can conclude with an escalation sender module commanding an escalation handler to implement a security countermeasure. The flexible paths can therefore handle different types of alerts.