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公开(公告)号：US20230059755A1
公开(公告)日：2023-02-23
申请号：US17886026
申请日：2022-08-11
发明人： Shrijeet Mukherjee , Shimon Muller , Carlo Contavalli , Gurjeet Singh , Ariel Hendel , Rochan Sankar
摘要： A system for congestion control using a flow level transmit mechanism is disclosed. In some embodiments, the system comprises a source SFA and a receive SFA. The source SFA is configured to detect and classify a congestion notification packet (CNP) generated based on congestion in a network; select a receive block from a plurality of receive blocks based on the CNP; forward the CNP to a dedicated congestion notification queue of the receive block; identify a transmit queue from a plurality of transmit blocks based on processing the congestion notification queue, wherein the transmit queue originated a particular transmit flow causing the congestion; and stop the transmit queue.
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公开(公告)号：US20220217085A1
公开(公告)日：2022-07-07
申请号：US17570261
申请日：2022-01-06
IPC分类号： H04L45/00 , H04L47/2483 , H04L47/30
摘要： A server fabric adapter (SFA) communication system is disclosed. In some embodiments, the SFA communication system comprises an SFA communicatively coupled to a plurality of controlling hosts, a plurality of endpoints, and a plurality of network ports. The SFA is configured to receive a network packet from a network port of the plurality of network ports; separate the network packet into different portions, each portion including a header or a payload; map each portion of the network packet to: (i) a controlling host of the plurality controlling hosts, the controlling host being designated as a destination controlling host, or (ii) an endpoint of the plurality of endpoints, the endpoint being designated as a destination endpoint; and forward a respective portion of the network packet to the destination controlling host or the destination endpoint.
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公开(公告)号：US20240264964A1
公开(公告)日：2024-08-08
申请号：US18639698
申请日：2024-04-18
发明人： Thomas Norrie , Shrijeet Mukherjee , John Greth , Rochan Sankar , Shimon Muller , Ariel Hendel , Gurjeet Singh
IPC分类号： G06F13/40
CPC分类号： G06F13/4022 , G06F2213/0026
摘要： A multi-plane, multi-protocol memory switch system is disclosed. In some embodiments, a memory switch includes a plurality of switch ports, the memory switch connectable to one or more root complex (RC) devices through one or more respective switch ports of the plurality of switch ports, and the memory switch connectable to a set of endpoints through a set of other switch ports of the plurality of switch ports, wherein the set includes zero or multiple endpoints; a cacheline exchange engine configured to provide a data-exchange path between two endpoints and to map an address space of one endpoint to an address space of another endpoint; and a bulk data transfer engine configured to facilitate data-exchange between two endpoints as a source-destination data stream, one endpoint being designated a source address and another endpoint being designated a destination address.
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公开(公告)号：US20240244005A1
公开(公告)日：2024-07-18
申请号：US18096354
申请日：2023-01-12
发明人： Shrijeet Mukherjee , Carlo Contavalli , Shimon Muller , Ariel Hendel , Gurjeet Singh , Rochan Sankar
IPC分类号： H04L47/2483 , H04L47/41 , H04L47/62 , H04L49/901
CPC分类号： H04L47/2483 , H04L47/41 , H04L47/621 , H04L49/901 , H04L49/9068
摘要： An adaptive generic receive offload (A-GRO) system and method are disclosed. In some embodiments, the system comprises a host including a host protocol stack and a host memory, and a network interface card that is communicatively connectable to the host. The A-GRO system is configured to: receive a packet from a network, parse the packet to a header and a payload, classify and map the packet into a particular flow based on contexts associated with a plurality of flows and the header, and move the header and the payload to separate queues associated with the particular flow in the host memory, without holding and stalling the packet in hardware of the NIC. By maintain packet coherence information including header chains, the A-GRO allows the host to skip processing the packets between the first and last headers in a GRO aggregation. The A-GRO system also improves mis-ordering packet handling.
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公开(公告)号：US20240184732A1
公开(公告)日：2024-06-06
申请号：US18526727
申请日：2023-12-01
IPC分类号： H05K1/14
CPC分类号： H05K1/141 , H05K2201/04
摘要： A modular interconnection system is disclosed. In some embodiments, the modular interconnection system comprising a server fabric adapter (SFA) on a primary circuit board, the SFA configured to perform peripheral component interconnect express (PCIe) interconnection or compute express link (CXL) interconnection; a plurality of ports on one or more PCIe slots configured to connect the SFA to external resources; and a PCIe slot adaptation device configured to adapt a first lane count slot of the one or more PCIe slots to support a second lane count device.
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公开(公告)号：US20220398207A1
公开(公告)日：2022-12-15
申请号：US17835472
申请日：2022-06-08
发明人： Thomas Norrie , Shrijeet Mukherjee , John Greth , Rochan Sankar , Shimon Muller , Ariel Hendel , Gurjeet Singh
IPC分类号： G06F13/40
摘要： A multi-plane, multi-protocol memory switch system is disclosed. In some embodiments, a memory switch includes a plurality of switch ports, the memory switch connectable to one or more root complex (RC) devices through one or more respective switch ports of the plurality of switch ports, and the memory switch connectable to a set of endpoints through a set of other switch ports of the plurality of switch ports, wherein the set includes zero or multiple endpoints; a cacheline exchange engine configured to provide a data-exchange path between two endpoints and to map an address space of one endpoint to an address space of another endpoint; and a bulk data transfer engine configured to facilitate data-exchange between two endpoints as a source-destination data stream, one endpoint being designated a source address and another endpoint being designated a destination address.
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公开(公告)号：US20240345989A1
公开(公告)日：2024-10-17
申请号：US18755372
申请日：2024-06-26
发明人： Thomas Norrie , Shrijeet Mukherjee , Rochan Sankar
IPC分类号： G06F15/173 , H04L9/08
CPC分类号： G06F15/17331 , H04L9/0863
摘要： A system for providing memory access is disclosed. In some embodiments, the system is configured to receive at a source server fabric adapter (SFA), from a server, a memory access request comprising a virtual memory address; using associative mapping, determining whether the virtual address corresponds to a source-local memory associated with the source SFA or to a remote memory. If the virtual address corresponds to the source-local memory, the virtual memory address is translated, at the source SFA, into a physical memory address of the source-local memory. If the virtual address corresponds to the remote memory, a request message is synthesized, and the synthesized request message is transmitted to the destination SFA using a network protocol.
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公开(公告)号：US12120021B2
公开(公告)日：2024-10-15
申请号：US17570261
申请日：2022-01-06
IPC分类号： H04L49/9057 , H04L45/00 , H04L47/2483 , H04L47/30 , H04L69/22
CPC分类号： H04L45/566 , H04L45/38 , H04L47/2483 , H04L47/30 , H04L49/9057 , H04L69/22
摘要： A server fabric adapter (SFA) communication system is disclosed. In some embodiments, the SFA communication system comprises an SFA communicatively coupled to a plurality of controlling hosts, a plurality of endpoints, and a plurality of network ports. The SFA is configured to receive a network packet from a network port of the plurality of network ports; separate the network packet into different portions, each portion including a header or a payload; map each portion of the network packet to: (i) a controlling host of the plurality controlling hosts, the controlling host being designated as a destination controlling host, or (ii) an endpoint of the plurality of endpoints, the endpoint being designated as a destination endpoint; and forward a respective portion of the network packet to the destination controlling host or the destination endpoint.
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公开(公告)号：US20240330221A1
公开(公告)日：2024-10-03
申请号：US18742729
申请日：2024-06-13
发明人： Thomas Norrie , Shrijeet Mukherjee , John Greth , Rochan Sankar , Shimon Muller , Ariel Hendel , Gurjeet Singh
IPC分类号： G06F13/40
CPC分类号： G06F13/4022 , G06F2213/0026
摘要： A multi-plane, multi-protocol memory switch system is disclosed. In some embodiments, a memory switch includes a plurality of switch ports, the memory switch connectable to one or more root complex (RC) devices through one or more respective switch ports of the plurality of switch ports, and the memory switch connectable to a set of endpoints through a set of other switch ports of the plurality of switch ports, wherein the set includes zero or multiple endpoints; a cacheline exchange engine configured to provide a data-exchange path between two endpoints and to map an address space of one endpoint to an address space of another endpoint; and a bulk data transfer engine configured to facilitate data-exchange between two endpoints as a source-destination data stream, one endpoint being designated a source address and another endpoint being designated a destination address.
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公开(公告)号：US11995017B2
公开(公告)日：2024-05-28
申请号：US17835472
申请日：2022-06-08
发明人： Thomas Norrie , Shrijeet Mukherjee , John Greth , Rochan Sankar , Shimon Muller , Ariel Hendel , Gurjeet Singh
IPC分类号： G06F13/40
CPC分类号： G06F13/4022 , G06F2213/0026
摘要： A multi-plane, multi-protocol memory switch system is disclosed. In some embodiments, a memory switch includes a plurality of switch ports, the memory switch connectable to one or more root complex (RC) devices through one or more respective switch ports of the plurality of switch ports, and the memory switch connectable to a set of endpoints through a set of other switch ports of the plurality of switch ports, wherein the set includes zero or multiple endpoints; a cacheline exchange engine configured to provide a data-exchange path between two endpoints and to map an address space of one endpoint to an address space of another endpoint; and a bulk data transfer engine configured to facilitate data-exchange between two endpoints as a source-destination data stream, one endpoint being designated a source address and another endpoint being designated a destination address.
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