公开(公告)号：US07613990B1

公开(公告)日：2009-11-03

申请号：US10717042

申请日：2003-11-18

Applicant: William A. Wilkie ,  David I. Lawrie ,  Elizabeth R. Cowie

Inventor： William A. Wilkie ,  David I. Lawrie ,  Elizabeth R. Cowie

IPC: H03M13/00 ,  G06F11/00 ,  G01R31/30

CPC classification number: H03M13/3922 ,  H03M13/3966

Abstract: A circuit for a multi-channel add-compare-select unit is disclosed. The circuit includes a compare unit and a datapath. The datapath is coupled to the compare unit, and includes a number of adder units, a selection unit (which is coupled to the adder units), and a number of clocked storage stages.

Abstract translation: 公开了一种用于多通道加法比较选择单元的电路。 该电路包括比较单元和数据通路。 数据路径耦合到比较单元，并且包括多个加法器单元，选择单元（其耦合到加法器单元）和多个计时存储级。

公开(公告)号：US07895507B1

公开(公告)日：2011-02-22

申请号：US11707311

申请日：2007-02-16

Applicant: Elizabeth R. Cowie ,  David I. Lawrie

Inventor： Elizabeth R. Cowie ,  David I. Lawrie

IPC: H03M13/41

CPC classification number: H03M13/4107

Abstract: An Add-Compare-Select circuit for use with a trellis decoder can include a first module and a second module. The first module can provide a difference signal specifying an indication of a difference between a second path cost and a first path cost of a trellis. The second path cost can be a sum of a second state cost and a second branch metric and the first path cost can be a sum of a first state cost and a first branch metric. The second module can select the first path cost or the second path cost as a new cost according to the difference signal of the first module.

Abstract translation: 用于网格解码器的加法比较选择电路可以包括第一模块和第二模块。 第一模块可以提供指定网格的第二路径成本和第一路径开销之间的差的指示的差分信号。 第二路径成本可以是第二状态成本和第二分支量度的总和，并且第一路径成本可以是第一状态成本和第一分支度量的和。 第二模块可以根据第一模块的差信号选择第一路径开销或第二路径开销作为新成本。

公开(公告)号：US08843807B1

公开(公告)日：2014-09-23

申请号：US13212997

申请日：2011-08-18

Applicant: Colin Stirling ,  David I. Lawrie ,  David Andrews

Inventor： Colin Stirling ,  David I. Lawrie ,  David Andrews

IPC: H03M13/00 ,  H03M13/03 ,  H03M13/41

CPC classification number: H03M13/4107 ,  H03M13/2987 ,  H03M13/6505 ,  H03M13/6525

Abstract: In one embodiment, a circular pipeline processing system is provided. The system includes a plurality of processing stages configured to operate in a circular pipeline. Each processing stage is configured to output a fully processed data block in response to completing a final processing iteration, and otherwise, store a partially processed data block in a memory buffer of the processing stage. Each processing stage is configured to select between an unprocessed data block and a partially processed data block from the memory buffer of a preceding processing stage, based on one or more of availability of memory sufficient for storage of an unprocessed data block or availability of a partially processed data block. The processing stage is configured to process the selected data block.

Abstract translation: 在一个实施例中，提供了一种圆形流水线处理系统。 该系统包括被配置为在圆形管道中操作的多个处理级。 每个处理阶段被配置为响应于完成最终处理迭代而输出完全处理的数据块，否则，将部分处理的数据块存储在处理级的存储器缓冲器中。 每个处理阶段被配置为基于一个或多个足够存储未处理的数据块的存储器的可用性或部分地处理的数据块的可用性来选择来自前一处理级的存储器缓冲器的未处理数据块和部分处理的数据块 处理后的数据块。 处理阶段被配置为处理所选择的数据块。

公开(公告)号：US07810010B1

公开(公告)日：2010-10-05

申请号：US11439667

申请日：2006-05-24

Applicant: David I. Lawrie

Inventor： David I. Lawrie

IPC: H03M13/00

CPC classification number: H03M13/3922 ,  H03M13/3723 ,  H03M13/3972

Abstract: A Turbo Code decoder for implementation in an integrated circuit is described. An add-compare select (“ACS”) unit is configured to provide a difference between first and second outputs and to select one of the first and second outputs responsive to a difference thereof. An initialization stage is coupled to receive and configured to store for example the first output selected as an initialization value. A second select stage is coupled to receive for example the first output selected from the first select stage and coupled to obtain the initialization value stored from the initialization stage. The second select stage is configured to output either the first output selected from the ACS unit or the initialization value from the initialization stage.

Abstract translation: 描述了用于在集成电路中实现的Turbo码解码器。 加法比较选择（“ACS”）单元被配置为提供第一和第二输出之间的差异，并且响应于其差异来选择第一和第二输出中的一个。 耦合初始化阶段以接收和配置为存储例如被选择为初始化值的第一输出。 第二选择级被耦合以接收例如从第一选择级选择的第一输出并被耦合以获得从初始化阶段存储的初始化值。 第二选择级被配置为从初始化阶段输出从ACS单元选择的第一输出或初始化值。

公开(公告)号：US20100070737A1

公开(公告)日：2010-03-18

申请号：US12233320

申请日：2008-09-18

Applicant: Colin Stirling ,  David I. Lawrie ,  David Andrews

Inventor： Colin Stirling ,  David I. Lawrie ,  David Andrews

IPC: G06F12/06

CPC classification number: G06F9/345 ,  G06F9/3455 ,  G06F9/3552 ,  G06F9/3875 ,  H03M13/2739

Abstract: Address generation by an integrated circuit is described. An aspect relates generally to an address generator which has first and second processing units. The second processing unit is coupled to receive a stage output from the first processing unit and configured to provide an address output. The stage output is in a first range, and the address output is in a second range. The first range is from −K to −1 for K a block size, and the second range is from 0 to K-1.

Abstract translation: 描述了由集成电路产生的地址。 一方面涉及具有第一和第二处理单元的地址发生器。 第二处理单元被耦合以从第一处理单元接收级输出并且被配置为提供地址输出。 舞台输出处于第一范围，地址输出处于第二范围。 对于K块，第一个范围从-K到-1，第二个范围是从0到K-1。

公开(公告)号：US09003266B1

公开(公告)日：2015-04-07

申请号：US13088303

申请日：2011-04-15

Applicant: Colin Stirling ,  David I. Lawrie ,  David Andrews

Inventor： Colin Stirling ,  David I. Lawrie ,  David Andrews

IPC: H03M13/00 ,  H03M13/15

CPC classification number: H03M13/1555 ,  H03M13/2987

Abstract: In one embodiment, a method of block decoding is provided. For each of a plurality of data blocks input to a memory arrangement, a plurality of decoding iterations are performed using a circular pipeline of processing stages. For each decoding iteration, one processing stage of the circular pipeline performs a first set and a second set of soft-input-soft-output (SISO) decoding operations on a block of data. The first set of SISO decoding operations produces an intermediate block of data. The second set of SISO decoding operations is performed on the intermediate data block to complete the one decoding iteration. The next decoding iteration of the plurality of decoding iterations is performed using the next processing stage following the one processing stage of the circular pipeline of processing stages.

Abstract translation: 在一个实施例中，提供了块解码的方法。 对于输入到存储器装置的多个数据块中的每一个，使用处理级的循环管线执行多个解码迭代。 对于每个解码迭代，循环流水线的一个处理阶段对数据块执行第一组和第二组软输入软输出（SISO）解码操作。 第一组SISO解码操作产生中间的数据块。 在中间数据块上执行第二组SISO解码操作，以完成一次解码迭代。 使用处理阶段的圆形流水线的一个处理阶段之后的下一个处理阶段来执行多个解码迭代的下一个解码迭代。

公开(公告)号：US08332735B1

公开(公告)日：2012-12-11

申请号：US12400694

申请日：2009-03-09

Applicant: David Andrews ,  David I. Lawrie ,  Colin Stirling

Inventor： David Andrews ,  David I. Lawrie ,  Colin Stirling

IPC: H03M13/00

CPC classification number: H03M13/3911 ,  H03M13/3922 ,  H03M13/6502

Abstract: A method for decoding an encoded message is described. The method includes obtaining a set of metrics which includes first and second state metrics, and first and second branch metrics. First and second offset values for the iteration are obtained. The first state and branch metrics are added together to obtain a first partial result. The second state and branch metrics are added together to obtain a second partial result. The second partial result is subtracted from the first partial result to obtain a difference. The first partial result and the first offset value are added together to obtain a first result. The second partial result and the second offset value are added together to obtain a second result. Either the first result or the second result is selected for output responsive to the difference. A log correction term is selected responsive to the difference.

Abstract translation: 描述用于解码编码消息的方法。 该方法包括获得包括第一和第二状态度量以及第一和第二分支度量的一组度量。 获得迭代的第一和第二偏移值。 将第一个状态和分支度量相加在一起以获得第一部分结果。 将第二状态和分支度量相加在一起以获得第二部分结果。 从第一部分结果中减去第二部分结果以获得差异。 将第一部分结果和第一偏移值相加在一起以获得第一结果。 将第二部分结果和第二偏移值相加在一起以获得第二结果。 选择第一结果或第二结果来响应差异来选择输出。 响应于差异来选择对数校正项。

公开(公告)号：US08219782B2

公开(公告)日：2012-07-10

申请号：US12233320

申请日：2008-09-18

Applicant: Colin Stirling ,  David I. Lawrie ,  David Andrews

Inventor： Colin Stirling ,  David I. Lawrie ,  David Andrews

IPC: G06F12/06

CPC classification number: G06F9/345 ,  G06F9/3455 ,  G06F9/3552 ,  G06F9/3875 ,  H03M13/2739

Abstract: Address generation by an integrated circuit is described. An aspect relates generally to an address generator which has first and second processing units. The second processing unit is coupled to receive a stage output from the first processing unit and configured to provide an address output. The stage output is in a first range, and the address output is in a second range. The first range is from −K to −1 for K a block size, and the second range is from 0 to K−1.

Abstract translation: 描述了由集成电路产生的地址。 一方面涉及具有第一和第二处理单元的地址发生器。 第二处理单元被耦合以从第一处理单元接收级输出并且被配置为提供地址输出。 舞台输出处于第一范围，地址输出处于第二范围。 对于K块，第一个范围从-K到-1，第二个范围是从0到K-1。