PROVIDING A FEEDBACK LOOP IN A LOW LATENCY SERIAL INTERCONNECT ARCHITECTURE
    1.
    发明申请
    PROVIDING A FEEDBACK LOOP IN A LOW LATENCY SERIAL INTERCONNECT ARCHITECTURE 失效
    在低延迟串行互连架构中提供反馈环路

    公开(公告)号:US20130241751A1

    公开(公告)日:2013-09-19

    申请号:US13781039

    申请日:2013-02-28

    IPC分类号: H03M9/00

    CPC分类号: H03M9/00 H04J3/0608

    摘要: In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase control signal received from a feedback loop coupled between the de-serializer and a receiver logic coupled to an output of the de-serializer. Other embodiments are described and claimed.

    摘要翻译: 在一个实施例中,本发明包括解串器,用于以第一速率接收串行数据,并且响应于从反馈回路接收的相位控制信号,输出与对准边界对准的串行数据的并行数据帧 耦合在解串器和耦合到解串器的输出的接收器逻辑之间。 描述和要求保护其他实施例。